Test per flip-flop type

diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
index 05e68caf7e91a6d02759be09648055a44b26025f..223b52d21965c30861549fb802fdae34b8c275c9 100644 (file)
--- a/tests/xilinx/adffs.v
+++ b/tests/xilinx/adffs.v
@@ -45,43 +45,3 @@ module ndffnr
                else
             q <= d;
 endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 961e08ae9ed958efdc8b92c7a09915d677b19f58..7edab67c728c449e32c0c1a19be74d38b8b26742 100644 (file)
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,14 +1,44 @@
 read_verilog adffs.v
+design -save read
+
 proc
-flatten
-equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-none t:BUFG t:FDCE %% t:* %D
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-count 1 t:LUT1
+select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDCE
 select -assert-count 1 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE_1
-select -assert-count 1 t:LUT1
-select -assert-count 2 t:LUT2
-select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
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