ac/llvm: improve sync scope for global atomics

Stronger ordering is implemented in SPIRV->NIR with barriers.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index ddf9f09fe0cf670185f8ffdd1bd8b64e4aeb27e6..830866bc5cb898995ed4429f731e3ff7fde15fb3 100644 (file)
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -3024,6 +3024,9 @@ static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
 
        nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
        if (deref->mode == nir_var_mem_global) {
+               /* use "singlethread" sync scope to implement relaxed ordering */
+               sync_scope = LLVM_VERSION_MAJOR >= 9 ? "singlethread-one-as" : "singlethread";
+
                LLVMTypeRef ptr_type = LLVMPointerType(LLVMTypeOf(src), LLVMGetPointerAddressSpace(LLVMTypeOf(ptr)));
                ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ptr_type , "");
        }