fhdl/specials: allow setting memory name

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index 9d443aba9a1111cc6c377042b1df5ed2f96dfc80..e3c5099e59ae133e6e44e7dcf2d9daea1e3dcd60 100644 (file)
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -180,12 +180,13 @@ class _MemoryPort:
                self.clock_domain = clock_domain
 
 class Memory(Special):
-       def __init__(self, width, depth, init=None):
+       def __init__(self, width, depth, init=None, name="mem"):
                Special.__init__(self)
                self.width = width
                self.depth = depth
                self.ports = []
                self.init = init
+               self.name_override = name
        
        def get_port(self, write_capable=False, async_read=False,
          has_re=False, we_granularity=0, mode=WRITE_FIRST,
@@ -234,8 +235,6 @@ class Memory(Special):
                                add(p.dat_r)
                return s
 
-       name_override = "mem"
-
        @staticmethod
        def emit_verilog(memory, ns, clock_domains):
                r = ""