WIP

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ff3de65cceee132630a93ef5e51619ac2a06be92..e9b4f07bf857bbfc8741226858b05b1bf2f343d1 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -336,8 +336,6 @@ struct XAigerWriter
                                }
                        }
 
-                       bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
-
                        // Fully pad all unused input connections of this box cell with S0
                        // Fully pad all undriven output connections of this box cell with anonymous wires
                        for (auto port_name : r.first->second) {
@@ -615,65 +613,11 @@ struct XAigerWriter
                        if (holes_module) {
                                log_push();
 
-                               // NB: fixup_ports() will sort ports by name
-                               //holes_module->fixup_ports();
-                               holes_module->check();
-
-                               // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
-                               //   since boxes may contain parameters in which case `flatten` would have
-                               //   created a new $paramod ...
-                               Pass::call_on_module(holes_module->design, holes_module, "wbflip");
-                               Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
-
-                               dict<SigSig, SigSig> replace;
-                               for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
-                                       auto cell = it->second;
-                                       if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
-                                                               "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
-                                               SigBit D = cell->getPort("\\D");
-                                               SigBit Q = cell->getPort("\\Q");
-                                               // Remove the DFF cell from what needs to be a combinatorial box
-                                               it = holes_module->cells_.erase(it);
-                                               Wire *port;
-                                               if (GetSize(Q.wire) == 1)
-                                                       port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
-                                               else
-                                                       port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
-                                               log_assert(port);
-                                               // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
-                                               //   in order to extract the combinatorial control logic that feeds the box
-                                               //   (i.e. clock enable, synchronous reset, etc.)
-                                               replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
-                                               // Since `flatten` above would have created wires named "<cell>.Q",
-                                               //   extract the pre-techmap cell name
-                                               auto pos = Q.wire->name.str().rfind(".");
-                                               log_assert(pos != std::string::npos);
-                                               IdString driver = Q.wire->name.substr(0, pos);
-                                               // And drive the signal that was previously driven by "DFF.Q" (typically
-                                               //   used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
-                                               //   wire (which itself is driven an input port) we inserted above
-                                               Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
-                                               log_assert(currQ);
-                                               holes_module->connect(Q, currQ);
-                                               continue;
-                                       }
-                                       else if (!cell->type.in("$_NOT_", "$_AND_"))
-                                               log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
-                                       ++it;
-                               }
-
-                               for (auto &conn : holes_module->connections_) {
-                                       auto it = replace.find(conn);
-                                       if (it != replace.end())
-                                               conn = it->second;
-                               }
-
                                // Move into a new (temporary) design so that "clean" will only
                                // operate (and run checks on) this one module
                                RTLIL::Design *holes_design = new RTLIL::Design;
                                module->design->modules_.erase(holes_module->name);
                                holes_design->add(holes_module);
-                               Pass::call(holes_design, "opt -purge");
 
                                std::stringstream a_buffer;
                                XAigerWriter writer(holes_module);

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index af37ecb5c33f31d28fc5a7e414d510b7a3f350f6..da56f42ea17d9182b8541d5b1a63fd47a6cd5bff 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -186,15 +186,17 @@ struct Abc9Pass : public ScriptPass
        void script() YS_OVERRIDE
        {
                run("scc -set_attr abc9_scc_id {}");
-               run("abc9_ops -break_scc"/*" -prep_holes"*/);
-//             run("flatten -wb @abc9_holes");
-//             run("techmap @abc9_holes");
+               run("abc9_ops -break_scc");
                run("aigmap");
+
                run("abc9_ops -prep_holes");
+               run("select -set abc9_holes A:abc9_holes");
+               run("flatten -wb @abc9_holes");
+               run("techmap @abc9_holes");
+               run("aigmap @abc9_holes");
                if (dff_mode)
                        run("abc9_ops -prep_dff");
-//             run("opt -purge @abc9_holes");
-               run("select -set abc9_holes A:abc9_holes");
+               run("opt -purge @abc9_holes");
                run("wbflip @abc9_holes");
 
                auto selected_modules = active_design->selected_modules();

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index bcf622dbae7352188bd957eaf7d192fb9b50c797..632f2bc8a5c9ce0aa8bd255dd28ac668431dd6e8 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -386,8 +386,6 @@ void prep_holes(RTLIL::Module *module)
                        }
                }
 
-               // NB: Assume box_module->ports are sorted alphabetically
-               //     (as RTLIL::Module::fixup_ports() would do)
                for (const auto &port_name : box_ports.at(cell->type)) {
                        RTLIL::Wire *w = box_module->wire(port_name);
                        log_assert(w);