ARM: Keep a copy of the fpscr len and stride fields in the decoder.

Avoid reading them every instruction, and also eliminate the last use of the
thread context in the decoders.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 4001f7597b1e5fc1ab0b7e61b7d97147be2142b7..b5a73d68b9dff1e7a286dd4a8bd17a6cad92a523 100644 (file)
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -113,9 +113,8 @@ Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     data = inst;
     offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
     emi.thumb = pc.thumb();
-    FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
-    emi.fpscrLen = fpscr.len;
-    emi.fpscrStride = fpscr.stride;
+    emi.fpscrLen = fpscrLen;
+    emi.fpscrStride = fpscrStride;
 
     outOfBytes = false;
     process();

diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index a5f2c88a572e0cd4f8bf20ad9f9aa1bd6c880ed4..9099e3e2e2baa49db510e74b8e066513c4d3815c 100644 (file)
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -58,6 +58,9 @@ class Decoder
     bool foundIt;
     ITSTATE itBits;
 
+    int fpscrLen;
+    int fpscrStride;
+
   public:
     void reset()
     {
@@ -69,7 +72,8 @@ class Decoder
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0)
+    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
+        fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
@@ -121,6 +125,12 @@ class Decoder
         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
     }
 
+    void setContext(FPSCR fpscr)
+    {
+        fpscrLen = fpscr.len;
+        fpscrStride = fpscr.stride;
+    }
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b253574c76fd5032f308cd3c55d56fd25ed980ab..0df50a85e526472337c874259f88ba9b5151bc78 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -381,6 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
+                tc->getDecodePtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:

diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 37a46b052d66a82f2f35d11eefa446dabf912f52..4078630d69f5cf1ea2f3528e564ee0a0dea5c8a0 100644 (file)
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -293,7 +293,7 @@ RemoteGDB::setregs()
     }
 
     //FPSCR
-    context->setMiscRegNoEffect(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
+    context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
 }
 
 void