default = Self.badaddr_responder.pio
-def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxAlphaSystem(mem_mode, mdesc = None):
IO_address_space_base = 0x80000000000
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
# base address (including the PCI config space)
self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
- self.physmem = MemClass(range = AddrRange(mdesc.mem()))
- self.mem_ranges = [self.physmem.range]
+ self.mem_ranges = [AddrRange(mdesc.mem())]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
return self
-def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
-
- physmem = MemClass(range = AddrRange(mdesc.mem()))
- self = LinuxAlphaSystem(physmem = physmem)
- self.mem_ranges = [self.physmem.range]
+ self = LinuxAlphaSystem()
+ self.mem_ranges = [AddrRange(mdesc.mem())]
if not mdesc:
# generic system
mdesc = SysConfig()
# Create pio bus to connect all device pio ports to rubymem's pio port
self.piobus = NoncoherentBus()
- #
- # Pio functional accesses from devices need direct access to memory
- # RubyPort currently does support functional accesses. Therefore provide
- # the piobus a direct connection to physical memory
- #
- self.piobus.master = physmem.port
-
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
return self
-def makeSparcSystem(mem_mode, MemClass, mdesc = None):
+def makeSparcSystem(mem_mode, mdesc = None):
# Constants from iob.cc and uart8250.cc
iob_man_addr = 0x9800000000
uart_pio_size = 8
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
- self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
- self.mem_ranges = [self.physmem.range, self.physmem2.range]
+ self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
+ AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
- self.physmem2.port = self.membus.master
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
self.hypervisor_desc.port = self.membus.master
return self
-def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
+def makeArmSystem(mem_mode, machine_type, mdesc = None,
dtb_filename = None, bare_metal=False):
assert machine_type
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
- self.mem_ranges = [self.physmem.range]
+ self.mem_ranges = [AddrRange(mdesc.mem())]
else:
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
if dtb_filename is not None:
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
-
- self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
- size = mdesc.mem()),
- conf_table_reported = True)
- self.mem_ranges = [self.physmem.range]
+ self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
+ size = mdesc.mem())]
self.realview.setupBootLoader(self.membus, self, binary)
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().lower().count('android'):
boot_flags += " init=/init "
self.boot_osflags = boot_flags
-
- self.physmem.port = self.membus.master
self.realview.attachOnChipIO(self.membus, self.bridge)
self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
return self
-def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
+def makeLinuxMipsSystem(mem_mode, mdesc = None):
class BaseMalta(Malta):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
self.iobus = NoncoherentBus()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
- self.physmem = MemClass(range = AddrRange('1GB'))
- self.mem_ranges = [self.physmem.range]
+ self.mem_ranges = [AddrRange('1GB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
- self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
APIC_range_size = 1 << 12;
x86_sys.membus = MemBus()
- x86_sys.physmem.port = x86_sys.membus.master
# North Bridge
x86_sys.iobus = NoncoherentBus()
# North Bridge
x86_sys.piobus = NoncoherentBus()
- #
- # Pio functional accesses from devices need direct access to memory
- # RubyPort currently does support functional accesses. Therefore provide
- # the piobus a direct connection to physical memory
- #
- x86_sys.piobus.master = x86_sys.physmem.port
# add the ide to the list of dma devices that later need to attach to
# dma controllers
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
-def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
+def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
Ruby = False):
if self == None:
self = X86System()
self.mem_mode = mem_mode
# Physical memory
- self.physmem = MemClass(range = AddrRange(mdesc.mem()))
- self.mem_ranges = [self.physmem.range]
+ self.mem_ranges = [AddrRange(mdesc.mem())]
# Platform
self.pc = Pc()
self.intel_mp_table.base_entries = base_entries
self.intel_mp_table.ext_entries = ext_entries
-def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
+def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
Ruby = False):
self = LinuxX86System()
# Build up the x86 system and then specialize it for Linux
- makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
+ makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
# We assume below that there's at least 1MB of memory. We'll require 2
# just to avoid corner cases.
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- self.memories.unproxy(self)))
+ phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
assert(phys_mem_size >= 0x200000)
self.e820_table.entries = \
np = options.num_cpus
if buildEnv['TARGET_ISA'] == "alpha":
- test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
+ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "mips":
- test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
+ test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
- test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
+ test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
- test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
- options.num_cpus, bm[0])
+ test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
elif buildEnv['TARGET_ISA'] == "arm":
- test_sys = makeArmSystem(test_mem_mode, options.machine_type,
- TestMemClass, bm[0], options.dtb_filename,
+ test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
+ options.dtb_filename,
bare_metal=options.bare_metal)
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
CacheConfig.config_cache(options, test_sys)
+# Create the appropriate memory controllers and connect them to the
+# memory bus
+test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
+ for r in test_sys.mem_ranges]
+for i in xrange(len(test_sys.mem_ctrls)):
+ test_sys.mem_ctrls[i].port = test_sys.membus.master
+
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
- drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
+ drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips':
- drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
+ drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'sparc':
- drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
+ drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
- drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
+ drive_sys = makeX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
- drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
- DriveMemClass, bm[1])
+ drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
# Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
+ # Create the appropriate memory controllers and connect them to the
+ # memory bus
+ drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
+ for r in drive_sys.mem_ranges]
+ for i in xrange(len(drive_sys.mem_ctrls)):
+ drive_sys.mem_ctrls[i].port = drive_sys.membus.master
+
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
TestMemClass = Simulation.setMemClass(options)
if buildEnv['TARGET_ISA'] == "alpha":
- system = makeLinuxAlphaRubySystem(test_mem_mode, TestMemClass, bm[0])
+ system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
- system = makeLinuxX86System(test_mem_mode, TestMemClass,
- options.num_cpus, bm[0], True)
+ system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
Simulation.setWorkCountOptions(system, options)
else:
fatal("incapable of building non-alpha or non-x86 full system!")
system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+# Create the appropriate memory controllers and connect them to the
+# PIO bus
+system.mem_ctrls = [TestMemClass(range = r,
+ conf_table_reported = True)
+ for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+ system.mem_ctrls[i].port = system.piobus.master
+
root = Root(full_system = True, system = system)
Simulation.run(options, root, system, FutureClass)
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
cntrl_count += 1
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
total_mem_size.value += dir_cntrl.directory.size.value
dir_cntrl.directory.numa_high_bit = numa_bit
- phys_mem_size = sum(map(lambda mem: mem.range.size(),
- system.memories.unproxy(system)))
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(total_mem_size.value == phys_mem_size)
ruby_profiler = RubyProfiler(ruby_system = ruby,
pass
def create_system(self):
- system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+ system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
self.init_system(system)
return system
def create_system(self):
system = FSConfig.makeArmSystem(self.mem_mode,
- self.machine_type,
- DDR3_1600_x64,
- None, False)
+ self.machine_type, None, False)
# We typically want the simulator to panic if the kernel
# panics or oopses. This prevents the simulator from running
def init_system(self, system):
BaseSystem.init_system(self, system)
+ # create the memory controllers and connect them, stick with
+ # the physmem name to avoid bumping all the reference stats
+ system.physmem = [self.mem_class(range = r,
+ conf_table_reported = True)
+ for r in system.mem_ranges]
+ for i in xrange(len(system.physmem)):
+ system.physmem[i].port = system.membus.master
+
# create the iocache, which by default runs at the system clock
system.iocache = IOCache(addr_ranges=system.mem_ranges)
system.iocache.cpu_side = system.iobus.master
for cpu in cpus:
cpu.clk_domain = system.cpu_clk_domain
+system.mem_ranges = AddrRange('256MB')
+
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU).create_root()
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='atomic',
+ mem_class=DDR3_1600_x64,
cpu_class=AtomicSimpleCPU).create_root()
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
-system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
+system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
mdesc=mdesc, Ruby=True)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
# Set access_phys_mem to True for ruby port
system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+system.physmem = [DDR3_1600_x64(range = r,
+ conf_table_reported = True)
+ for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+ system.physmem[i].port = system.piobus.master
+
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=TimingSimpleCPU).create_root()
import switcheroo
root = LinuxX86FSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU,
checker=True).create_root()
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
+ cpu_class=DerivO3CPU,
num_cpus=2).create_root()
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU).create_root()
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='atomic',
+ mem_class=DDR3_1600_x64,
+ cpu_class=AtomicSimpleCPU,
num_cpus=2).create_root()
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
+ mem_class=DDR3_1600_x64,
cpu_class=AtomicSimpleCPU).create_root()
from m5.objects import *
from arm_generic import *
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
+ cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()
from arm_generic import *
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=TimingSimpleCPU).create_root()
import switcheroo
root = LinuxArmFSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
).create_root()
import switcheroo
root = LinuxArmFSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()
import switcheroo
root = LinuxArmFSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(DerivO3CPU, DerivO3CPU)
).create_root()
import switcheroo
root = LinuxArmFSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
).create_root()
system = System(tester = tester, physmem = SimpleMemory(null = True),
clk_domain = SrcClockDomain(clock = options.sys_clock))
+system.mem_ranges = AddrRange('256MB')
+
Ruby.create_system(options, system)
# Create a separate clock domain for Ruby
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+system.mem_ranges = AddrRange('256MB')
+
Ruby.create_system(options, system)
# Create a separate clock for Ruby
m5.util.addToPath('../configs/common')
import FSConfig
-system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
+system = FSConfig.makeSparcSystem('atomic')
system.clk_domain = SrcClockDomain(clock = '1GHz')
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
+# create the memory controllers and connect them, stick with
+# the physmem name to avoid bumping all the reference stats
+system.physmem = [SimpleMemory(range = r,
+ conf_table_reported = True)
+ for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+ system.physmem[i].port = system.membus.master
+
root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('2GHz')
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=InOrderCPU).create_root()
from m5.objects import *
from alpha_generic import *
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
+ cpu_class=DerivO3CPU,
num_cpus=2).create_root()
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=DerivO3CPU).create_root()
from m5.objects import *
from alpha_generic import *
-root = LinuxAlphaFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='atomic',
+ mem_class=DDR3_1600_x64,
+ cpu_class=AtomicSimpleCPU,
num_cpus=2).create_root()
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic',
+ mem_class=DDR3_1600_x64,
cpu_class=AtomicSimpleCPU).create_root()
from m5.objects import *
from alpha_generic import *
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
+ cpu_class=TimingSimpleCPU,
num_cpus=2).create_root()
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_x64,
cpu_class=TimingSimpleCPU).create_root()
import switcheroo
root = LinuxAlphaFSSwitcheroo(
+ mem_class=DDR3_1600_x64,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
).create_root()
from FSConfig import *
from Benchmarks import *
-test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
- SysConfig('netperf-stream-client.rcS'))
+test_sys = makeLinuxAlphaSystem('atomic',
+ SysConfig('netperf-stream-client.rcS'))
# Create the system clock domain
test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
+test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
+test_sys.physmem.port = test_sys.membus.master
+
+drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS'))
# Create the system clock domain
drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
+drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
+drive_sys.physmem.port = drive_sys.membus.master
+
root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
maxtick = 199999999
def create_system(self):
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
- DDR3_1600_x64,
numCPUs=self.num_cpus,
mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
projects / gem5.git / commitdiff