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synth_ecp5: use +/abc9_model.v
authorEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 17:56:52 +0000 (09:56 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 27 Feb 2020 18:17:29 +0000 (10:17 -0800)
techlibs/ecp5/synth_ecp5.cc patch | blob | history

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 463ddb5caab5dc30c13bdddf4b7a892672666347..9916fdafb45fb6373b384422636ac813d1a14961 100644 (file)
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -322,7 +322,7 @@ struct SynthEcp5Pass : public ScriptPass
                                run("techmap " + techmap_args);
 
                        if (abc9) {
-                               run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
+                               run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
                                if (nowidelut)
                                        run("abc9 -maxlut 4 -W 200");
                                else