re PR target/59290 ([ARM] regression on negdi-2.c (big-endian))

[gcc/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* config/arm/arm.md (*zextendsidi_negsi): New pattern.
	* config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
	for zero_extend case.

[gcc/testsuite/]
2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	PR target/59290
	* gcc.target/arm/negdi-2.c: Scan more general register names.

From-SVN: r205394

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d63759e2c8c7f6f6c85212d0f3e16db282506eea..61cbbc4def0dc87cf14146f524a290c6fde82004 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/59290
+       * config/arm/arm.md (*zextendsidi_negsi): New pattern.
+       * config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly
+       for zero_extend case.
+
 2013-11-26   H.J. Lu  <hongjiu.lu@intel.com>
 
        PR bootstrap/55552

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4af6c05949f255001fd042af8132747d3bfd3b6f..f88ebbc1536321682d53de90459d4856ac241196 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -10130,6 +10130,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
          if (speed_p)
            *cost += 2 * extra_cost->alu.shift;
        }
+      else  /* GET_MODE (XEXP (x, 0)) == SImode.  */
+        *cost = COSTS_N_INSNS (1);
 
       /* Widening beyond 32-bits requires one more insn.  */
       if (mode == DImode)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 16095fabdf4b45069e5f7a084aa5b5d4e06ad47a..dd733668168373070836c1150fb9bf312441c1a8 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4718,6 +4718,24 @@
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
   "")
 
+(define_insn_and_split "*zextendsidi_negsi"
+  [(set (match_operand:DI 0 "s_register_operand" "=r")
+        (zero_extend:DI (neg:SI (match_operand:SI 1 "s_register_operand" "r"))))]
+   "TARGET_32BIT"
+   "#"
+   ""
+   [(set (match_dup 2)
+         (neg:SI (match_dup 1)))
+    (set (match_dup 3)
+         (const_int 0))]
+   {
+      operands[2] = gen_lowpart (SImode, operands[0]);
+      operands[3] = gen_highpart (SImode, operands[0]);
+   }
+ [(set_attr "length" "8")
+  (set_attr "type" "multiple")]
+)
+
 ;; Negate an extended 32-bit value.
 (define_insn_and_split "*negdi_extendsidi"
   [(set (match_operand:DI 0 "s_register_operand" "=l,r")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2ae530032a1c90778071b60c665caed995cc4cbf..84abf1d2f645cfe508cfa2d7e395ccd91b90707f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/59290
+       * gcc.target/arm/negdi-2.c: Scan more general register names.
+
 2013-11-26  Terry Guo  <terry.guo@arm.com>
 
        * gcc.target/arm/thumb1-pic-high-reg.c: New case.

diff --git a/gcc/testsuite/gcc.target/arm/negdi-2.c b/gcc/testsuite/gcc.target/arm/negdi-2.c
index 96bbcab337e54cdb072fc11f19cf412b56b463a5..4444c20ea9c010e7f5de67a953730efa680146b3 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/negdi-2.c
+++ b/gcc/testsuite/gcc.target/arm/negdi-2.c
@@ -11,6 +11,6 @@ Expected output:
        rsb     r0, r0, #0
        mov     r1, #0
 */
-/* { dg-final { scan-assembler-times "rsb\\tr0, r0, #0" 1 { target { arm_nothumb } } } } */
-/* { dg-final { scan-assembler-times "negs\\tr0, r0" 1 { target { ! arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */
 /* { dg-final { scan-assembler-times "mov" 1 } } */