*
*/
-`define INPUT_A input [A_WIDTH-1:0] A; \
- generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate
-
-`define INPUT_B input [B_WIDTH-1:0] B; \
- generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate
-
// --------------------------------------------------------
module \$not (A, Y);
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
+input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-assign Y = ~A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = ~$signed(A);
+ end else begin:BLOCK2
+ assign Y = ~A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
+input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
generate
if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:BLOCK1
- assign Y[A_WIDTH-1:0] = A_BUF.val;
+ assign Y[A_WIDTH-1:0] = A;
assign Y[Y_WIDTH-1:A_WIDTH] = 0;
- end else begin:BLOCK2
- assign Y = +A_BUF.val;
+ end else if (A_SIGNED) begin:BLOCK2
+ assign Y = $signed(A);
+ end else begin:BLOCK3
+ assign Y = A;
end
endgenerate
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
+input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-assign Y = +A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = $signed(A);
+ end else begin:BLOCK2
+ assign Y = A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
+input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-assign Y = -A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = -$signed(A);
+ end else begin:BLOCK2
+ assign Y = -A;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val & B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) & $signed(B);
+ end else begin:BLOCK2
+ assign Y = A & B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val | B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) | $signed(B);
+ end else begin:BLOCK2
+ assign Y = A | B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val ^ B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) ^ $signed(B);
+ end else begin:BLOCK2
+ assign Y = A ^ B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val ~^ B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) ~^ $signed(B);
+ end else begin:BLOCK2
+ assign Y = A ~^ B;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-output Y;
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
-assign Y = &A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = &$signed(A);
+ end else begin:BLOCK2
+ assign Y = &A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-output Y;
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
-assign Y = |A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = |$signed(A);
+ end else begin:BLOCK2
+ assign Y = |A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-output Y;
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
-assign Y = ^A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = ^$signed(A);
+ end else begin:BLOCK2
+ assign Y = ^A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-output Y;
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
-assign Y = ~^A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = ~^$signed(A);
+ end else begin:BLOCK2
+ assign Y = ~^A;
+ end
+endgenerate
endmodule
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-output Y;
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val != 0;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = !(!$signed(A));
+ end else begin:BLOCK2
+ assign Y = !(!A);
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val << B_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) << B;
+ end else begin:BLOCK2
+ assign Y = A << B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val >> B_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) >> B;
+ end else begin:BLOCK2
+ assign Y = A >> B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val <<< B_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) <<< B;
+ end else begin:BLOCK2
+ assign Y = A <<< B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val >>> B_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) >>> B;
+ end else begin:BLOCK2
+ assign Y = A >>> B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val < B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) < $signed(B);
+ end else begin:BLOCK2
+ assign Y = A < B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val <= B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) <= $signed(B);
+ end else begin:BLOCK2
+ assign Y = A <= B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val == B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) == $signed(B);
+ end else begin:BLOCK2
+ assign Y = A == B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val != B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) != $signed(B);
+ end else begin:BLOCK2
+ assign Y = A != B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val === B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) === $signed(B);
+ end else begin:BLOCK2
+ assign Y = A === B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val !== B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) !== $signed(B);
+ end else begin:BLOCK2
+ assign Y = A !== B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val >= B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) >= $signed(B);
+ end else begin:BLOCK2
+ assign Y = A >= B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val > B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) > $signed(B);
+ end else begin:BLOCK2
+ assign Y = A > B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val + B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) + $signed(B);
+ end else begin:BLOCK2
+ assign Y = A + B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val - B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) - $signed(B);
+ end else begin:BLOCK2
+ assign Y = A - B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val * B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) * $signed(B);
+ end else begin:BLOCK2
+ assign Y = A * B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val / B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) / $signed(B);
+ end else begin:BLOCK2
+ assign Y = A / B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val % B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) % $signed(B);
+ end else begin:BLOCK2
+ assign Y = A % B;
+ end
+endgenerate
endmodule
// --------------------------------------------------------
+`ifndef SIMLIB_NOPOW
module \$pow (A, B, Y);
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val ** B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) ** $signed(B);
+ end else if (A_SIGNED) begin:BLOCK2
+ assign Y = $signed(A) ** B;
+ end else if (B_SIGNED) begin:BLOCK3
+ assign Y = A ** $signed(B);
+ end else begin:BLOCK4
+ assign Y = A ** B;
+ end
+endgenerate
endmodule
+`endif
// --------------------------------------------------------
module \$logic_not (A, Y);
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
+input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-assign Y = !A_BUF.val;
+generate
+ if (A_SIGNED) begin:BLOCK1
+ assign Y = !$signed(A);
+ end else begin:BLOCK2
+ assign Y = !A;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val && B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) && $signed(B);
+ end else begin:BLOCK2
+ assign Y = A && B;
+ end
+endgenerate
endmodule
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
-`INPUT_A
-`INPUT_B
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-assign Y = A_BUF.val || B_BUF.val;
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign Y = $signed(A) || $signed(B);
+ end else begin:BLOCK2
+ assign Y = A || B;
+ end
+endgenerate
endmodule