(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index d2bfbb44a82164815d5fd8f5af4d7d9f151ec15b..700ac943cbb97a22c7b691b12c27f45228f2befc 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -4,6 +4,7 @@
 
 * v0.00 05may2021 first created
 * v0.01 06may2021 initial first draft
+* v0.02 08may2021 add scenarios / use-cased
 
 **Table of Contents**
 
@@ -842,27 +843,23 @@ TLB entries to the PE in response.
 
 **Use-case: Matrix and Convolutions**
 
+* **Horizontal-First**: (aka standard Cray Vectors) walk
+  through **elements** first before moving to next instruction
+* **Vertical-First**: walk through **instructions** before
+  moving to next element.  Currently managed by `svstep`,
+  ZOLC may be deployed to manage the stepping.
+
 Imagine a large Matrix scenario, with several values close to zero that
 could be skipped: no need to include zero-multiplications, but a
 traditional CPU in no way can help: only by loading the data through
 the L1-L4 Cache and Virtual Memory Barriers is it possible to
 ascertain, retrospectively, that time and power had just been wasted.
 
-SVP64 is able to do what is termed "Vertical-First" Vectorisation
-*(walk first through a batch of instructions before explicitly
-moving to the next element with `svstep`, and repeating the batch)*,
+SVP64 is able to do what is termed "Vertical-First" Vectorisation,
 combined with SVREMAP Matrix Schedules.  Imagine that SVREMAP has been
 extended, Snitch-style, to perform a deterministic memory-array walk of
 a large Matrix.
 
-*<blockquote>
-* **Horizontal-First**: (aka standard Cray Vectors) walk through
-  **elements** first before moving to next instruction
-* **Vertical-First**: walk through **instructions** before
-  moving to next element.  Currently managed by `svstep`,
-  ZOLC may be deployed to manage the stepping.
-</blockquote>*
-
 Let us also imagine that the Matrices are stored in Memory with PEs
 attached, and that the PEs are fully functioning Power ISA with Draft
 SVP64, but their Multiply capability is not as good as the main CPU.