(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index edbf7b6c17291eff0e4d7f173998ae8a0aac1c54..b6ee4150ddc929b714dda30218ff34303ef0a148 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -239,7 +239,7 @@ instruction.
 
 *Packed SIMD looped algorithms actually have to
 contain multiple implementations processing fragments of data at
-different SIMD widths: Cray-style Vectors have one, covering not
+different SIMD widths: Cray-style Vectors have just the one, covering not
 just current architectural implementations but future ones with
 wider back-end ALUs as well.*