boards/targets/minispartan6: for now revert experimental s6pll clocking

diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 9f745282db9021f4d8012ac8e2e7fd1c5c91478f..20e2113e4f14ae3e4a9173ccbc8c1b342b266205 100755 (executable)
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -18,7 +18,7 @@ from litedram.phy import GENSDRPHY
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, clk_freq):
+    def __init__(self, platform, clk_freq, use_s6pll=False):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
 
@@ -27,10 +27,50 @@ class _CRG(Module):
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys_ps.clk.attr.add("keep")
 
-        self.submodules.pll = pll = S6PLL(speedgrade=-1)
-        pll.register_clkin(platform.request("clk32"), 32e6)
-        pll.create_clkout(self.cd_sys, clk_freq)
-        pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
+        if use_s6pll:
+            self.submodules.pll = pll = S6PLL(speedgrade=-1)
+            pll.register_clkin(platform.request("clk32"), 32e6)
+            pll.create_clkout(self.cd_sys, clk_freq)
+            pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
+        else:
+            f0 = 32*1000000
+            clk32 = platform.request("clk32")
+            clk32a = Signal()
+            self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
+            clk32b = Signal()
+            self.specials += Instance("BUFIO2", p_DIVIDE=1,
+                                      p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
+                                      i_I=clk32a, o_DIVCLK=clk32b)
+            f = Fraction(int(clk_freq), int(f0))
+            n, m, p = f.denominator, f.numerator, 8
+            assert f0/n*m == clk_freq
+            pll_lckd = Signal()
+            pll_fb = Signal()
+            pll = Signal(6)
+            self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
+                                         p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
+                                         p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
+                                         i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
+                                         p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
+                                         i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
+                                         p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
+                                         i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
+                                         o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
+                                         o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
+                                         o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
+                                         o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
+                                         o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
+                                         o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
+                                         p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
+                                         p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
+                                         p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
+                                         p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
+                                         p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,  # sys
+                                         p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1,  # sys_ps
+            )
+            self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
+            self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
+            self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
 
         self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
                                   p_INIT=0, p_SRTYPE="SYNC",