projects / binutils-gdb.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 1db1303)
RISC-V: xtheadfmemidx: Use fp register in mnemonics
authorChristoph Müllner <christoph.muellner@vrull.eu>
Mon, 7 Nov 2022 12:46:20 +0000 (13:46 +0100)
committerNelson Chu <nelson@rivosinc.com>
Wed, 9 Nov 2022 02:46:07 +0000 (10:46 +0800)
Although the encoding for scalar and fp registers is identical,
we should follow common pratice and use fp register names
when referencing fp registers.

The xtheadmemidx extension consists of indirect load/store instructions
which all load to or store from fp registers.
Let's use fp register names in this case and adjust the test cases
accordingly.

gas/
    * testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to
    be float register.
    * testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise.
    * testsuite/gas/riscv/x-thead-fmemidx.d: Likewise.
    * testsuite/gas/riscv/x-thead-fmemidx.s: Likewise.
opcodes/
    * riscv-opc.c (riscv_opcodes): Updated since rd need to be float register.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l patch | blob | history
gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s patch | blob | history
gas/testsuite/gas/riscv/x-thead-fmemidx.d patch | blob | history
gas/testsuite/gas/riscv/x-thead-fmemidx.s patch | blob | history
opcodes/riscv-opc.c patch | blob | history

diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l
index ef28f047b41c77254237fd4fc877f4bce60fa931..33cddac856e5b944664bf874b664f4d15d4890c5 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l
+++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l
@@ -1,4 +1,5 @@
 .*: Assembler messages:
+.*: Error: illegal operands `th.flrd a0,a1,a2,0'
 .*: Error: improper immediate value \(18446744073709551615\)
 .*: Error: improper immediate value \(4\)
 .*: Error: improper immediate value \(18446744073709551615\)
diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s
index e486c6a14239ead2c67b5dd25861bc0e3a35022a..8c6ee0cda4cb35a1f160f62892c8fe1b501204e3 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s
+++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s
@@ -1,17 +1,18 @@
 target:
-       th.flrd         a0, a1, a2, -1
-       th.flrd         a0, a1, a2, 4
-       th.flrw         a0, a1, a2, -1
-       th.flrw         a0, a1, a2, 4
-       th.flurd        a0, a1, a2, -1
-       th.flurd        a0, a1, a2, 4
-       th.flurw        a0, a1, a2, -1
-       th.flurw        a0, a1, a2, 4
-       th.fsrd         a0, a1, a2, -1
-       th.fsrd         a0, a1, a2, 4
-       th.fsrw         a0, a1, a2, -1
-       th.fsrw         a0, a1, a2, 4
-       th.fsurd        a0, a1, a2, -1
-       th.fsurd        a0, a1, a2, 4
-       th.fsurw        a0, a1, a2, -1
-       th.fsurw        a0, a1, a2, 4
+       th.flrd         a0, a1, a2, 0
+       th.flrd         fa0, a1, a2, -1
+       th.flrd         fa0, a1, a2, 4
+       th.flrw         fa0, a1, a2, -1
+       th.flrw         fa0, a1, a2, 4
+       th.flurd        fa0, a1, a2, -1
+       th.flurd        fa0, a1, a2, 4
+       th.flurw        fa0, a1, a2, -1
+       th.flurw        fa0, a1, a2, 4
+       th.fsrd         fa0, a1, a2, -1
+       th.fsrd         fa0, a1, a2, 4
+       th.fsrw         fa0, a1, a2, -1
+       th.fsrw         fa0, a1, a2, 4
+       th.fsurd        fa0, a1, a2, -1
+       th.fsurd        fa0, a1, a2, 4
+       th.fsurw        fa0, a1, a2, -1
+       th.fsurw        fa0, a1, a2, 4
diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.d b/gas/testsuite/gas/riscv/x-thead-fmemidx.d
index dfa477c8fc4b09d312276ed03f23ece4cd4c30b9..e8d53a339516589a3b4b3238b29eefdf34dd3522 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-fmemidx.d
+++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.d
@@ -7,19 +7,19 @@
 Disassembly of section .text:
 
 0+000 <target>:
-[      ]+[0-9a-f]+:[   ]+60c5e50b[     ]+th.flrd[      ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+66c5e50b[     ]+th.flrd[      ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+40c5e50b[     ]+th.flrw[      ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+46c5e50b[     ]+th.flrw[      ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+70c5e50b[     ]+th.flurd[     ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+76c5e50b[     ]+th.flurd[     ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+50c5e50b[     ]+th.flurw[     ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+56c5e50b[     ]+th.flurw[     ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+60c5f50b[     ]+th.fsrd[      ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+66c5f50b[     ]+th.fsrd[      ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+40c5f50b[     ]+th.fsrw[      ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+46c5f50b[     ]+th.fsrw[      ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+70c5f50b[     ]+th.fsurd[     ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+76c5f50b[     ]+th.fsurd[     ]+a0,a1,a2,3
-[      ]+[0-9a-f]+:[   ]+50c5f50b[     ]+th.fsurw[     ]+a0,a1,a2,0
-[      ]+[0-9a-f]+:[   ]+56c5f50b[     ]+th.fsurw[     ]+a0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+60c5e50b[     ]+th.flrd[      ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+66c5e50b[     ]+th.flrd[      ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+40c5e50b[     ]+th.flrw[      ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+46c5e50b[     ]+th.flrw[      ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+70c5e50b[     ]+th.flurd[     ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+76c5e50b[     ]+th.flurd[     ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+50c5e50b[     ]+th.flurw[     ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+56c5e50b[     ]+th.flurw[     ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+60c5f50b[     ]+th.fsrd[      ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+66c5f50b[     ]+th.fsrd[      ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+40c5f50b[     ]+th.fsrw[      ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+46c5f50b[     ]+th.fsrw[      ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+70c5f50b[     ]+th.fsurd[     ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+76c5f50b[     ]+th.fsurd[     ]+fa0,a1,a2,3
+[      ]+[0-9a-f]+:[   ]+50c5f50b[     ]+th.fsurw[     ]+fa0,a1,a2,0
+[      ]+[0-9a-f]+:[   ]+56c5f50b[     ]+th.fsurw[     ]+fa0,a1,a2,3
diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.s b/gas/testsuite/gas/riscv/x-thead-fmemidx.s
index 0d70bb7e799414718303b60824a0fa6580b0563b..f26bdc332c8b31c50b81393d2a86dc55dfb7bc97 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-fmemidx.s
+++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.s
@@ -1,17 +1,17 @@
 target:
-       th.flrd         a0, a1, a2, 0
-       th.flrd         a0, a1, a2, 3
-       th.flrw         a0, a1, a2, 0
-       th.flrw         a0, a1, a2, 3
-       th.flurd        a0, a1, a2, 0
-       th.flurd        a0, a1, a2, 3
-       th.flurw        a0, a1, a2, 0
-       th.flurw        a0, a1, a2, 3
-       th.fsrd         a0, a1, a2, 0
-       th.fsrd         a0, a1, a2, 3
-       th.fsrw         a0, a1, a2, 0
-       th.fsrw         a0, a1, a2, 3
-       th.fsurd        a0, a1, a2, 0
-       th.fsurd        a0, a1, a2, 3
-       th.fsurw        a0, a1, a2, 0
-       th.fsurw        a0, a1, a2, 3
+       th.flrd         fa0, a1, a2, 0
+       th.flrd         fa0, a1, a2, 3
+       th.flrw         fa0, a1, a2, 0
+       th.flrw         fa0, a1, a2, 3
+       th.flurd        fa0, a1, a2, 0
+       th.flurd        fa0, a1, a2, 3
+       th.flurw        fa0, a1, a2, 0
+       th.flurw        fa0, a1, a2, 3
+       th.fsrd         fa0, a1, a2, 0
+       th.fsrd         fa0, a1, a2, 3
+       th.fsrw         fa0, a1, a2, 0
+       th.fsrw         fa0, a1, a2, 3
+       th.fsurd        fa0, a1, a2, 0
+       th.fsurd        fa0, a1, a2, 3
+       th.fsurw        fa0, a1, a2, 0
+       th.fsurw        fa0, a1, a2, 3
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4029c1881b875acd721a06aded9a0fd25327b03c..599486fdf03e61a0a1b448df13d33cc462e3896c 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1922,14 +1922,14 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.mvnez",         0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0},
 
 /* Vendor-specific (T-Head) XTheadFMemIdx instructions.  */
-{"th.flrd",    0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD,  MASK_TH_FLRD,  match_opcode, 0},
-{"th.flrw",    0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW,  MASK_TH_FLRW,  match_opcode, 0},
-{"th.flurd",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
-{"th.flurw",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
-{"th.fsrd",    0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD,  MASK_TH_FSRD,  match_opcode, 0},
-{"th.fsrw",    0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW,  MASK_TH_FSRW,  match_opcode, 0},
-{"th.fsurd",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
-{"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
+{"th.flrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRD,  MASK_TH_FLRD,  match_opcode, 0},
+{"th.flrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRW,  MASK_TH_FLRW,  match_opcode, 0},
+{"th.flurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0},
+{"th.flurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0},
+{"th.fsrd",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRD,  MASK_TH_FSRD,  match_opcode, 0},
+{"th.fsrw",    0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRW,  MASK_TH_FSRW,  match_opcode, 0},
+{"th.fsurd",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0},
+{"th.fsurw",   0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
 
 /* Vendor-specific (T-Head) XTheadMemIdx instructions.  */
 {"th.ldia",  64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA,  MASK_TH_LDIA,  match_th_load_inc, 0},