Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 90d1b3fc41d740ea80696686457fef06f981c25b..edb6809ee968b43eba2ee55f36acbed129ec34b8 100644 (file)
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -118,7 +118,7 @@ struct BlifDumper
                for (auto &it : inputs) {
                        RTLIL::Wire *wire = it.second;
                        for (int i = 0; i < wire->width; i++)
-                               fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
+                               fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
                }
                fprintf(f, "\n");
 
@@ -126,7 +126,7 @@ struct BlifDumper
                for (auto &it : outputs) {
                        RTLIL::Wire *wire = it.second;
                        for (int i = 0; i < wire->width; i++)
-                               fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
+                               fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
                }
                fprintf(f, "\n");
 

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index bb2b26e26594b478ee52e94ac742440ee2301b26..f003c750d526b02ebdfc3b83486fa546bb0d8f88 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -271,7 +271,7 @@ struct EdifBackend : public Backend {
                                } else {
                                        fprintf(f, "          (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
                                        for (int i = 0; i < wire->width; i++) {
-                                               RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
+                                               RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i));
                                                net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
                                        }
                                }

diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index e4d12f3a152ee1ab98c45b162b2eb61f62225d72..dcb51d44d8e44e695874af6cfe3528af3635474f 100644 (file)
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -369,13 +369,13 @@ sigspec:
        TOK_ID '[' TOK_INT ']' {
                if (current_module->wires.count($1) == 0)
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-               $$ = new RTLIL::SigSpec(current_module->wires[$1], 1, $3);
+               $$ = new RTLIL::SigSpec(RTLIL::SigSpec::grml(current_module->wires[$1], $3));
                free($1);
        } |
        TOK_ID '[' TOK_INT ':' TOK_INT ']' {
                if (current_module->wires.count($1) == 0)
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-               $$ = new RTLIL::SigSpec(current_module->wires[$1], $3 - $5 + 1, $5);
+               $$ = new RTLIL::SigSpec(RTLIL::SigSpec::grml(current_module->wires[$1], $5, $3 - $5 + 1));
                free($1);
        } |
        '{' sigspec_list '}' {

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index acfba057fdfea794565c6a9b2bbca6df38299ffb..f5b84bc66b2a9efc2e1e277b04d0b4488d056475 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1331,13 +1331,6 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
        this->offset = 0;
 }
 
-RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int width, int offset)
-{
-       this->wire = wire;
-       this->width = width >= 0 ? width : wire->width;
-       this->offset = offset;
-}
-
 RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
 {
        RTLIL::SigChunk chunk;
@@ -1455,13 +1448,6 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
        check();
 }
 
-RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int width, int offset)
-{
-       chunks_.push_back(RTLIL::SigChunk(wire, width, offset));
-       width_ = chunks_.back().width;
-       check();
-}
-
 RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
 {
        RTLIL::SigSpec sig;
@@ -2166,7 +2152,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
                        std::vector<std::string> index_tokens;
                        sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
                        if (index_tokens.size() == 1)
-                               sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str())));
+                               sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str())));
                        else {
                                int a = atoi(index_tokens.at(0).c_str());
                                int b = atoi(index_tokens.at(1).c_str());
@@ -2174,7 +2160,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
                                        int tmp = a;
                                        a = b, b = tmp;
                                }
-                               sig.append(RTLIL::SigSpec(wire, b-a+1, a));
+                               sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1));
                        }
                } else
                        sig.append(wire);

diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index e93780b49e3ab337b0fdc7d128ba0759bd5b3ebd..d011b0ef5985905af0f61911d8f8d32d92609e17 100644 (file)
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -144,7 +144,7 @@ struct SigPool
        {
                RTLIL::SigSpec sig;
                for (auto &bit : bits) {
-                       sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
+                       sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
                        break;
                }
                return sig;
@@ -154,7 +154,7 @@ struct SigPool
        {
                RTLIL::SigSpec sig;
                for (auto &bit : bits)
-                       sig.append(RTLIL::SigSpec(bit.first, 1, bit.second));
+                       sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
                sig.sort_and_unify();
                return sig;
        }

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index e7371ec526668215bc6835ddf446326df9d0db37..fa2c496043d8ef60dcb29503515ed25ddfdcb4fb 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        clk_str = clk_str.substr(1);
                }
                if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
-                       clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0));
+                       clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0));
        }
 
        if (dff_mode && clk_sig.size() == 0)

diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index f8ffee52300d478d01b0eba9453b8792680ded75..1ac9664ad2df8f9c370477fb286d5d427933a7e1 100644 (file)
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
        RTLIL::SigSpec cases_vector;
 
        for (int in_state : fullstate_cache)
-               cases_vector.append(RTLIL::SigSpec(state_onehot, 1, in_state));
+               cases_vector.append(RTLIL::SigSpec::grml(state_onehot, in_state));
 
        for (auto &it : pattern_cache)
        {
@@ -47,7 +47,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
                for (int in_state : it.second)
                        if (fullstate_cache.count(in_state) == 0)
-                               or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
+                               or_sig.append(RTLIL::SigSpec::grml(state_onehot, in_state));
                or_sig.optimize();
 
                if (or_sig.size() == 0)
@@ -215,7 +215,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
                for (size_t j = 0; j < state.bits.size(); j++)
                        if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
-                               sig_a.append(RTLIL::SigSpec(state_wire, 1, j));
+                               sig_a.append(RTLIL::SigSpec::grml(state_wire, j));
                                sig_b.append(RTLIL::SigSpec(state.bits[j]));
                        }
                sig_a.optimize();
@@ -223,7 +223,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
                if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
                {
-                       module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, 1, i), sig_a));
+                       module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(state_onehot, i), sig_a));
                }
                else
                {
@@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                        eq_cell->type = "$eq";
                        eq_cell->connections["\\A"] = sig_a;
                        eq_cell->connections["\\B"] = sig_b;
-                       eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
+                       eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(state_onehot, i);
                        eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
                        eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
                        eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                fullstate_cache.erase(tr.state_in);
                }
 
-               implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, 1, i));
+               implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec::grml(next_state_onehot, i));
        }
 
        if (encoding_is_onehot)
@@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                if (state.bits[j] == RTLIL::State::S1)
                                        bit_idx = j;
                        if (bit_idx >= 0)
-                               next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, 1, i));
+                               next_state_sig.replace(bit_idx, RTLIL::SigSpec::grml(next_state_onehot, i));
                }
                log_assert(!next_state_sig.has_marked_bits());
                module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
@@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                sig_a = RTLIL::SigSpec(state);
                        } else {
                                sig_b.append(RTLIL::SigSpec(state));
-                               sig_s.append(RTLIL::SigSpec(next_state_onehot, 1, i));
+                               sig_s.append(RTLIL::SigSpec::grml(next_state_onehot, i));
                        }
                }
 

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 5c349f7027bd05730fd2b59afb97186d16afd6da..45c01f74a93617b6a230d27cbbd51d128f2be23f 100644 (file)
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -613,7 +613,7 @@ struct MemoryShareWorker
                                        groups_en[key] = grouped_en->width;
                                        grouped_en->width++;
                                }
-                               en.append(RTLIL::SigSpec(grouped_en, 1, groups_en[key]));
+                               en.append(RTLIL::SigSpec::grml(grouped_en, groups_en[key]));
                        }
 
                        module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 68fb2e72c3f61c61f2e3d998f9e17928741c0573..165bb25c962fb1bc4df58b35112027164748c85a 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
        for (auto &it : module->wires) {
                RTLIL::Wire *wire = it.second;
                for (int i = 0; i < wire->width; i++) {
-                       RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
+                       RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1);
                        if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
                                assign_map.add(s1);
                }

diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 50ba8fa1e82f8ff50013e9fdd1d3e1a49b1c87ac..0fe7657320b15e9b1dcbd4c47486ef3cbd27142b 100644 (file)
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
                if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
                {
-                       mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++), sig));
+                       mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig));
                }
                else
                {
@@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
                        eq_cell->connections["\\A"] = sig;
                        eq_cell->connections["\\B"] = comp;
-                       eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, 1, cmp_wire->width++);
+                       eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++);
                }
        }
 

diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 73235e930d4bc4551a1c31080adc92afaf0be492..91b428126af7c679f9f6c6349627834a3405e0b6 100644 (file)
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -260,8 +260,8 @@ struct VlogHammerReporter
                                for (int i = 0; i < int(inputs.size()); i++) {
                                        RTLIL::Wire *wire = module->wires.at(inputs[i]);
                                        for (int j = input_widths[i]-1; j >= 0; j--) {
-                                               ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
-                                               recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
+                                               ce.set(RTLIL::SigSpec::grml(wire, j), bits.back());
+                                               recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j));
                                                recorded_set_vals.bits.push_back(bits.back());
                                                bits.pop_back();
                                        }

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 79857c5ea4b96192e22d881632920c254570365f..51cf3ae0dbf16f4029ab9ae4720c1e35871e6d4a 100644 (file)
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
                                        eqx_cell->parameters["\\Y_WIDTH"] = 1;
                                        eqx_cell->parameters["\\A_SIGNED"] = 0;
                                        eqx_cell->parameters["\\B_SIGNED"] = 0;
-                                       eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, 1, i);
+                                       eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i);
                                        eqx_cell->connections["\\B"] = RTLIL::State::Sx;
                                        eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
                                        miter_module->add(eqx_cell);

diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 724bc3f985152ee67aa407fd85376662042a1d31..c209e8ed71b9f72e5c39c9327dd98623ba357171 100644 (file)
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -292,8 +292,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        module->add(supercell);
 
-                       RTLIL::SigSpec new_y1(y, y1.size(), 0);
-                       RTLIL::SigSpec new_y2(y, y2.size(), 0);
+                       RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
+                       RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -405,8 +405,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        supercell->check();
 
-                       RTLIL::SigSpec new_y1(y, y1.size(), 0);
-                       RTLIL::SigSpec new_y2(y, y2.size(), 0);
+                       RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
+                       RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -620,7 +620,7 @@ struct ShareWorker
                RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
                for (auto &p : activation_patterns) {
                        all_cases_wire->width++;
-                       module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, 1, all_cases_wire->width - 1));
+                       module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1));
                }
                if (all_cases_wire->width == 1)
                        return all_cases_wire;

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 5a7298087755e4ca625a2d1eeee016943772faa8..988917b17f624bec772f5fbdab2a775fbd2473d5 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -315,7 +315,7 @@ namespace
                        RTLIL::Wire *wire = it.second;
                        if (wire->port_id > 0) {
                                for (int i = 0; i < wire->width; i++)
-                                       sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i));
+                                       sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
                                cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
                        }
                }

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index eb2757f6679dfb8c386bfa6b04e1c649ff063c65..2cb76014cabcceed2cb606dd861609a627bf4bea 100644 (file)
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
                                                RTLIL::Cell *cell = new RTLIL::Cell;
                                                cell->name = NEW_ID;
                                                cell->type = RTLIL::escape_id(celltype);
-                                               cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i);
+                                               cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i);
                                                if (!portname2.empty())
-                                                       cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i);
+                                                       cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i);
                                                if (!widthparam.empty())
                                                        cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
                                                if (!nameparam.empty())