}
if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
out << " bool servicing_atomic;" << endl;
+ out << " bool started_receiving_writes;" << endl;
out << " Address locked_read_request1;" << endl;
out << " Address locked_read_request2;" << endl;
out << " Address locked_read_request3;" << endl;
out << "{ " << endl;
if (strncmp(component.c_str(), "L1Cache", 7) == 0) {
out << " servicing_atomic = false;" << endl;
+ out << " started_receiving_writes = false;" << endl;
out << " locked_read_request1 = Address(-1);" << endl;
out << " locked_read_request2 = Address(-1);" << endl;
out << " locked_read_request3 = Address(-1);" << endl;
} \n \
} \n \
else if (addr != locked_read_request1) { \n \
+ if (!started_receiving_writes) { \n \
if (locked_read_request2 == Address(-1)) { \n \
assert(read_counter == 1); \n \
locked_read_request2 = addr; \n \
// this can happen if there are multiple optimized consequtive shifts \n \
assert(0); \n \
} \n \
+ } \n \
} \n \
} \n \
else { \n \
locked_read_request3 = Address(-1); \n \
locked_read_request4 = Address(-1); \n \
servicing_atomic = false; \n \
+ started_receiving_writes = false; \n \
read_counter = 0; \n \
} \n \
} \n \
out << "void " << component << "_Controller::clear_atomic()" << endl;
out << "{" << endl;
out << " assert(servicing_atomic); " << endl;
+ out << " started_receiving_writes = true; " << endl;
out << " read_counter--; " << endl;
out << " if (read_counter == 0) { " << endl;
out << " servicing_atomic = false; " << endl;
+ out << " started_receiving_writes = false; " << endl;
out << " locked_read_request1 = Address(-1); " << endl;
out << " locked_read_request2 = Address(-1); " << endl;
out << " locked_read_request3 = Address(-1); " << endl;