ARM: Eliminate the unused rhi and rlo operands.

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 15499601ac2f2df0599ff15cba1978b985bbcc37..d13cca6dfab9c69650b2cb0184630d9a5129db9e 100644 (file)
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -96,8 +96,6 @@ enum IntRegIndex
 
     INTREG_ZERO, // Dummy zero reg since there has to be one.
     INTREG_UREG0,
-    INTREG_RHI,
-    INTREG_RLO,
     INTREG_CONDCODES,
 
     NUM_INTREGS,

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2621106ac7abab09080760d5df1f7cfc8370cc67..d80c0c7120562b20e84bb127d31150c6ce2c6673 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -109,8 +109,6 @@ def operands {{
     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
     'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
 
-    'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
-    'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
     'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
     'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),