integration/soc: add_ethernet: honor self.map["ethmac"], if present

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index c8abc75af0a0ef31187fbd3254ad0f6112606ece..aade79dbb2bfd36f99d61d12073738aeacc881ef 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1044,7 +1044,8 @@ class LiteXSoC(SoC):
             dw         = 32,
             interface  = "wishbone",
             endianness = self.cpu.endianness)
-        ethmac_region = SoCRegion(size=0x2000, cached=False)
+        ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None),
+                                  size=0x2000, cached=False)
         self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")