Ignore celldefine directive in verilog front-end

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 3a57514aa2ccab0d15f21c21d383481b3d07aba4..8fbaa953d7973d53b5a2d7a5a8282da1f59a17ba 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -116,6 +116,9 @@ YOSYS_NAMESPACE_END
 
 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 
+"`celldefine"[^\n]* /* ignore `celldefine */
+"`endcelldefine"[^\n]* /* ignore `endcelldefine */
+
 "`default_nettype"[ \t]+[^ \t\r\n/]+ {
        char *p = yytext;
        while (*p != 0 && *p != ' ' && *p != '\t') p++;