more slides

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 817e317af92b359979abca1b7c9ef8edb30ac8cc..56e99d01376b9299a863e9b90dada7eb5465fbd2 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -92,7 +92,7 @@ function op_add(rd, rs1, rs2, predr) # add not VADD!
   for (i=0; i < MIN(VL, vectorlen[rd]); i++)
     if (ireg[predr] & 1<<i) # predication uses intregs
        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-    if (reg_is_vectorised[rd]) \{ id += 1; \}
+    if (reg_is_vectorised[rd]) \{ id += 1; \}
     if (reg_is_vectorised[rs1]) \{ irs1 += 1; \}
     if (reg_is_vectorised[rs2]) \{ irs2 += 1; \}
 \end{semiverbatim}