#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace AlphaISA;
#ifndef __ARCH_ALPHA_PROCESS_HH__
#define __ARCH_ALPHA_PROCESS_HH__
+#include "mem/page_table.hh"
#include "sim/process.hh"
class AlphaLiveProcess : public LiveProcess
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include "arch/arm/intregs.hh"
#include "base/loader/object_file.hh"
+#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include <string>
#include <vector>
+#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;
#include "params/PowerInterrupts.hh"
#include "sim/sim_object.hh"
+class BaseCPU;
class ThreadContext;
namespace PowerISA {
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include <string>
#include <vector>
+#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;
* "Stub" to allow remote cpu to debug over a serial line using gdb.
*/
+
#include "arch/power/remote_gdb.hh"
#include <sys/signal.h>
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
+#include "mem/page_table.hh"
#include "sim/byteswap.hh"
using namespace std;
#include "params/RiscvInterrupts.hh"
#include "sim/sim_object.hh"
+class BaseCPU;
class ThreadContext;
namespace RiscvISA {
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include <string>
#include <vector>
+#include "mem/page_table.hh"
#include "sim/process.hh"
class LiveProcess;
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include <string>
#include <vector>
+#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process.hh"
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
+#include "base/compiler.hh"
#include "base/types.hh"
namespace LittleEndianGuest {}
#include <vector>
#include "base/bitunion.hh"
-#include "base/misc.hh"
#include "base/types.hh"
#include "base/trie.hh"
-#include "cpu/thread_context.hh"
#include "arch/x86/system.hh"
#include "debug/MMU.hh"
class Checkpoint;
+class ThreadContext;
namespace X86ISA
{
#include "mem/page_table.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
+#include "sim/syscall_return.hh"
#include "sim/system.hh"
using namespace std;
#include "arch/x86/pseudo_inst.hh"
#include "arch/x86/system.hh"
+#include "cpu/thread_context.hh"
#include "debug/PseudoInst.hh"
+#include "mem/se_translating_port_proxy.hh"
#include "sim/process.hh"
-#include "sim/system.hh"
using namespace X86ISA;
#include "arch/x86/system.hh"
-#include "arch/vtophys.hh"
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/bios/smbios.hh"
#include "arch/x86/isa_traits.hh"
-#include "arch/x86/regs/misc.hh"
-#include "base/intmath.hh"
#include "base/loader/object_file.hh"
-#include "base/loader/symtab.hh"
-#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "mem/port_proxy.hh"
#include "params/X86System.hh"
-#include "sim/byteswap.hh"
using namespace LittleEndianGuest;
using namespace X86ISA;
#include <vector>
#include "arch/x86/regs/misc.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/pc_event.hh"
-#include "kern/system_events.hh"
#include "params/X86System.hh"
-#include "sim/sim_object.hh"
#include "sim/system.hh"
namespace X86ISA
#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/insts/microldstop.hh"
-#include "arch/x86/pagetable.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/msr.hh"
#include "arch/x86/x86_traits.hh"
-#include "base/bitfield.hh"
#include "base/trace.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
-#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/full_system.hh"
#define __ARCH_X86_TLB_HH__
#include <list>
-#include <string>
#include <vector>
#include "arch/generic/tlb.hh"
-#include "arch/x86/regs/segment.hh"
#include "arch/x86/pagetable.hh"
#include "base/trie.hh"
-#include "mem/mem_object.hh"
#include "mem/request.hh"
#include "params/X86TLB.hh"
-#include "sim/sim_object.hh"
class ThreadContext;
-class Packet;
namespace X86ISA
{
#include "arch/x86/interrupts.hh"
#include "arch/x86/registers.hh"
-#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
#include "fputils/fp80.h"
-#include "sim/system.hh"
+#include "sim/full_system.hh"
namespace X86ISA {
#ifndef __ARCH_X86_UTILITY_HH__
#define __ARCH_X86_UTILITY_HH__
-#include "arch/x86/regs/misc.hh"
-#include "arch/x86/types.hh"
-#include "base/misc.hh"
-#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "sim/full_system.hh"
-class ThreadContext;
-
namespace X86ISA
{
#ifndef __BASE_BITFIELD_HH__
#define __BASE_BITFIELD_HH__
-#include "base/types.hh"
+#include <inttypes.h>
/**
* Generate a 64-bit mask of 'nbits' 1s, right justified.
#define __BASE_BITUNION_HH__
#include "base/bitfield.hh"
-#include "base/types.hh"
// The following implements the BitUnion system of defining bitfields
//on top of an underlying class. This is done through the pervasive use of
#include <iostream>
#include <sstream>
+#include "base/misc.hh"
#include "config/use_posix_clock.hh"
#include "sim/core.hh"
#include "sim/serialize.hh"
#include <sys/types.h>
-#include "base/output.hh" //simout
+#include "base/misc.hh"
+#include "base/output.hh"
#include "base/trace.hh"
#include "debug/VNC.hh"
#include <queue>
#include <sstream>
+#include "base/misc.hh"
#include "cpu/minor/trace.hh"
#include "cpu/activity.hh"
#include "cpu/timebuf.hh"
#include "cpu/testers/directedtest/InvalidateGenerator.hh"
+#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
+#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "debug/DirectedTest.hh"
#include "sim/sim_exit.hh"
#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "cpu/testers/directedtest/DirectedGenerator.hh"
#include "cpu/testers/directedtest/RubyDirectedTester.hh"
#include "debug/DirectedTest.hh"
#include "base/random.hh"
#include "base/statistics.hh"
+#include "base/trace.hh"
#include "debug/MemTest.hh"
#include "mem/mem_object.hh"
#include "sim/sim_exit.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "base/intmath.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "debug/RubyTest.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "base/misc.hh"
+#include "base/trace.hh"
#include "cpu/testers/rubytest/Check.hh"
#include "debug/RubyTest.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "dev/arm/flash_device.hh"
+#include "base/trace.hh"
#include "debug/Drain.hh"
/**
#define __DEV_MC146818_HH__
#include "base/bitunion.hh"
+#include "base/misc.hh"
#include "sim/eventq_impl.hh"
/** Real-Time Clock (MC146818) */
#include <thread>
#include <utility>
+#include "base/misc.hh"
#include "dev/net/dist_packet.hh"
#include "dev/net/etherpkt.hh"
#include "sim/core.hh"
#include <string>
#include <vector>
+#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#include "debug/EthernetData.hh"
#include "dev/net/etherswitch.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/EthernetAll.hh"
+#include "sim/core.hh"
using namespace std;
#include <list>
#include "base/statistics.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/GPUVRF.hh"
#include "gpu-compute/vector_register_state.hh"
#include <cstdio>
#include <string>
-#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "sim/process.hh"
#include "sim/system.hh"
#include <string>
#include "kern/operatingsystem.hh"
+#include "sim/process.hh"
class ThreadContext;
-class LiveProcess;
///
/// This class encapsulates the types, structures, constants,
#include "mem/cache/prefetch/stride.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
#include <cctype>
#include <iomanip>
+#include "base/trace.hh"
#include "debug/ExternalPort.hh"
std::map<std::string, ExternalMaster::Handler *>
#include <cctype>
#include <iomanip>
+#include "base/trace.hh"
#include "debug/ExternalPort.hh"
/** Implement a `stub' port which just responds to requests by printing
#include <vector>
#include "base/misc.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/MemChecker.hh"
#include "params/MemChecker.hh"
#include <string>
-#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
-#include "sim/serialize.hh"
-#include "sim/system.hh"
+
+class System;
/**
* This class implements an in-memory multi-level page table that can be
* @file
* Definitions of page table
*/
-#include <fstream>
-#include <map>
#include <string>
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
+#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "mem/multi_level_page_table.hh"
-#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "mem/page_table.hh"
using namespace std;
using namespace TheISA;
*/
#include "mem/page_table.hh"
-#include <fstream>
-#include <map>
-#include <memory>
#include <string>
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"
using namespace std;
using namespace TheISA;
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
+#include "base/intmath.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/serialize.hh"
-#include "sim/system.hh"
class ThreadContext;
+class System;
/**
* Declaration of base class for page table
#include <string>
#include <vector>
+#include "base/trace.hh"
#include "debug/RubyQueue.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
+#include "base/misc.hh"
+
AbstractReplacementPolicy::AbstractReplacementPolicy(const Params * p)
: SimObject(p)
{
#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
-#include "mem/page_table.hh"
#include "mem/port_proxy.hh"
+class PageTableBase;
class Process;
/**
#include "mem/simple_mem.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/Drain.hh"
using namespace std;
#include <Python.h>
+#include "base/misc.hh"
#include "sim/async.hh"
#include "sim/eventq.hh"
Source('syscall_emul.cc')
Source('syscall_desc.cc')
+if env['TARGET_ISA'] != 'x86':
+ Source('microcode_rom.cc')
+
DebugFlag('Checkpoint')
DebugFlag('Config')
DebugFlag('CxxConfig')
#include "arch/utility.hh"
#include "config/the_isa.hh"
-#include "cpu/thread_context.hh"
Arguments::Data::~Data()
{
#include <cassert>
#include <memory>
-#include "base/types.hh"
#include "mem/fs_translating_port_proxy.hh"
class ThreadContext;
#define __SIM_BYTE_SWAP_HH__
#include "base/bigint.hh"
-#include "base/misc.hh"
#include "base/types.hh"
// This lets us figure out what the byte order of the host system is
#include <algorithm>
#include <functional>
+#include "base/trace.hh"
#include "debug/ClockDomain.hh"
#include "params/ClockDomain.hh"
#include "params/DerivedClockDomain.hh"
#include "base/callback.hh"
#include "base/intmath.hh"
-#include "base/misc.hh"
#include "enums/PwrState.hh"
#include "params/ClockedObject.hh"
#include "sim/core.hh"
#include <string>
#include <vector>
-#include "mem/port.hh"
-#include "params/SimObject.hh"
#include "sim/sim_object.hh"
class CxxConfigParams;
#include "sim/cxx_config_ini.hh"
+#include "base/str.hh"
+
bool
CxxIniFile::getParam(const std::string &object_name,
const std::string ¶m_name,
#define __SIM_CXX_CONFIG_INI_HH__
#include "base/inifile.hh"
-#include "base/str.hh"
#include "sim/cxx_config.hh"
/** CxxConfigManager interface for using .ini files */
#include <sstream>
#include "base/str.hh"
+#include "base/trace.hh"
#include "debug/CxxConfig.hh"
#include "mem/mem_object.hh"
#include "sim/serialize.hh"
#include <mutex>
#include <unordered_set>
-#include "base/flags.hh"
-
class Drainable;
#ifndef SWIG // SWIG doesn't support strongly typed enums
#include <utility>
#include "base/misc.hh"
+#include "base/trace.hh"
#include "debug/DVFS.hh"
#include "params/DVFSHandler.hh"
#include "sim/clock_domain.hh"
+#include "sim/eventq_impl.hh"
#include "sim/stat_control.hh"
#include "sim/voltage_domain.hh"
d->perfLevel(perfLevelToSet);
}
+double
+DVFSHandler::voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
+{
+ VoltageDomain *d = findDomain(domain_id)->voltageDomain();
+ assert(d);
+ PerfLevel n = d->numVoltages();
+ if (perf_level < n)
+ return d->voltage(perf_level);
+
+ // Request outside of the range of the voltage domain
+ if (n == 1) {
+ DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
+ "voltage domain %s. Returning voltage at level 0: %.2f "\
+ "V\n", perf_level, d->name(), d->voltage(0));
+ // Special case for single point voltage domain -> same voltage for
+ // all points
+ return d->voltage(0);
+ }
+
+ warn("DVFSHandler %s reads illegal voltage level %u from "\
+ "VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
+ return 0.;
+}
+
void
DVFSHandler::serialize(CheckpointOut &cp) const
{
#include <vector>
#include "debug/DVFS.hh"
-#include "params/ClockDomain.hh"
#include "params/DVFSHandler.hh"
-#include "params/VoltageDomain.hh"
#include "sim/clock_domain.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
-#include "sim/voltage_domain.hh"
/**
* DVFS Handler class, maintains a list of all the domains it can handle.
* @return Voltage for the requested performance level of the respective
* domain
*/
- double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const
- {
- VoltageDomain *d = findDomain(domain_id)->voltageDomain();
- assert(d);
- PerfLevel n = d->numVoltages();
- if (perf_level < n)
- return d->voltage(perf_level);
-
- // Request outside of the range of the voltage domain
- if (n == 1) {
- DPRINTF(DVFS, "DVFS: Request for perf-level %i for single-point "\
- "voltage domain %s. Returning voltage at level 0: %.2f "\
- "V\n", perf_level, d->name(), d->voltage(0));
- // Special case for single point voltage domain -> same voltage for
- // all points
- return d->voltage(0);
- }
-
- warn("DVFSHandler %s reads illegal voltage level %u from "\
- "VoltageDomain %s. Returning 0 V\n", name(), perf_level, d->name());
- return 0.;
- }
+ double voltageAtPerfLevel(DomainID domain_id, PerfLevel perf_level) const;
/**
* Get the total number of available performance levels.
#include <string>
#include "base/flags.hh"
-#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Event.hh"
#include "sim/serialize.hh"
#include <ostream>
#include <string>
-#include "sim/emul_driver.hh"
+#include "sim/serialize.hh"
+
+class EmulatedDriver;
/**
* FDEntry is used to manage a single file descriptor mapping and metadata
#include "base/atomicio.hh"
#include "base/cprintf.hh"
+#include "base/misc.hh"
#include "sim/async.hh"
#include "sim/backtrace.hh"
#include "sim/core.hh"
#define __INSTRECORD_HH__
#include "base/bigint.hh"
-#include "base/trace.hh"
#include "base/types.hh"
-#include "cpu/inst_seq.hh" // for InstSeqNum
+#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"
--- /dev/null
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "sim/microcode_rom.hh"
+
+#include "base/misc.hh"
+#include "cpu/static_inst_fwd.hh"
+
+StaticInstPtr
+MicrocodeRom::fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
+{
+ panic("ROM based microcode isn't implemented.\n");
+}
* anything more.
*/
-#include "base/misc.hh"
-#include "cpu/static_inst.hh"
+#include <inttypes.h>
+
+#include "cpu/static_inst_fwd.hh"
+
+typedef uint16_t MicroPC;
class MicrocodeRom
{
public:
- StaticInstPtr
- fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop)
- {
- panic("ROM based microcode isn't implemented.\n");
- }
+ StaticInstPtr fetchMicroop(MicroPC micropc, StaticInstPtr curMacroop);
};
#endif // __SIM_MICROCODE_ROM_HH__
#include <unordered_map>
-#include "base/statistics.hh"
#include "params/MathExprPowerModel.hh"
#include "sim/mathexpr.hh"
#include "sim/power/power_model.hh"
-#include "sim/sim_object.hh"
+
+namespace Stats {
+ class Info;
+}
/**
* A Equation power model. The power is represented as a combination
#include "base/statistics.hh"
#include "params/PowerModel.hh"
#include "params/PowerModelState.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
#include "sim/sub_system.hh"
PowerModelState::PowerModelState(const Params *p)
#include "base/statistics.hh"
#include "params/PowerModel.hh"
#include "params/PowerModelState.hh"
-#include "sim/power/thermal_model.hh"
#include "sim/probe/probe.hh"
-#include "sim/sim_object.hh"
+
+class SimObject;
+class ClockedObject;
/**
* A PowerModelState is an abstract class used as interface to get power
#include "base/statistics.hh"
#include "debug/ThermalDomain.hh"
#include "params/ThermalDomain.hh"
+#include "sim/clocked_object.hh"
+#include "sim/linear_solver.hh"
#include "sim/power/thermal_model.hh"
-#include "sim/sim_object.hh"
+#include "sim/probe/probe.hh"
+#include "sim/sub_system.hh"
ThermalDomain::ThermalDomain(const Params *p)
: SimObject(p), _initTemperature(p->initial_temperature),
#include "base/statistics.hh"
#include "params/ThermalDomain.hh"
#include "sim/power/thermal_entity.hh"
-#include "sim/probe/probe.hh"
#include "sim/sim_object.hh"
-#include "sim/sub_system.hh"
+class SubSystem;
class ThermalNode;
+template <class T> class ProbePointArg;
/**
* A ThermalDomain is used to group objects under that operate under
#ifndef __SIM_THERMAL_ENTITY_HH__
#define __SIM_THERMAL_ENTITY_HH__
-#include "sim/linear_solver.hh"
-
+class LinearEquation;
class ThermalNode;
/**
#include <vector>
-#include "base/statistics.hh"
#include "params/ThermalCapacitor.hh"
#include "params/ThermalModel.hh"
#include "params/ThermalReference.hh"
#include "sim/probe/probe.hh"
#include "debug/ProbeVerbose.hh"
+#include "params/ProbeListenerObject.hh"
ProbePoint::ProbePoint(ProbeManager *manager, const std::string& _name)
: name(_name)
#include <string>
#include <vector>
+#include "base/compiler.hh"
#include "base/trace.hh"
-#include "params/ProbeListenerObject.hh"
#include "sim/sim_object.hh"
/** Forward declare the ProbeManager. */
class ProbeManager;
class ProbeListener;
+class ProbeListenerObjectParams;
/**
* Name space containing shared probe point declarations.
#include <fcntl.h>
#include <unistd.h>
-#include <cstdio>
+#include <array>
#include <map>
#include <string>
+#include <vector>
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
-#include "mem/multi_level_page_table.hh"
#include "mem/page_table.hh"
#include "mem/se_translating_port_proxy.hh"
#include "params/LiveProcess.hh"
#include "params/Process.hh"
-#include "sim/debug.hh"
-#include "sim/process_impl.hh"
-#include "sim/stats.hh"
+#include "sim/emul_driver.hh"
#include "sim/syscall_desc.hh"
#include "sim/system.hh"
#define __PROCESS_HH__
#include <array>
+#include <map>
#include <string>
#include <vector>
#include "mem/se_translating_port_proxy.hh"
#include "sim/fd_entry.hh"
#include "sim/sim_object.hh"
-#include "sim/syscall_return.hh"
-class PageTable;
-struct ProcessParams;
struct LiveProcessParams;
+struct ProcessParams;
+
+class EmulatedDriver;
+class PageTableBase;
class SyscallDesc;
+class SyscallReturn;
class System;
class ThreadContext;
-class EmulatedDriver;
template<class IntType>
struct AuxVector
#include <vector>
#include "mem/se_translating_port_proxy.hh"
-#include "sim/byteswap.hh"
//This needs to be templated for cases where 32 bit pointers are needed.
template<class AddrType>
* Gabe Black
*/
-#include "sim/root.hh"
-
#include "base/misc.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/TimeSync.hh"
+#include "sim/eventq_impl.hh"
#include "sim/full_system.hh"
+#include "sim/root.hh"
Root *Root::_root = NULL;
#include <vector>
#include "base/bitunion.hh"
-#include "base/types.hh"
+class CheckpointIn;
class IniFile;
class Serializable;
-class CheckpointIn;
class SimObject;
class SimObjectResolver;
-class EventQueue;
typedef std::ostream CheckpointOut;
#include <string>
#include "base/types.hh"
-#include "sim/core.hh"
+
+Tick curTick();
// forward declaration
class Callback;
#include "sim/sim_object.hh"
-#include <cassert>
-
-#include "base/callback.hh"
-#include "base/inifile.hh"
#include "base/match.hh"
#include "base/misc.hh"
#include "base/trace.hh"
-#include "base/types.hh"
#include "debug/Checkpoint.hh"
#include "sim/probe/probe.hh"
-#include "sim/stats.hh"
using namespace std;
#ifndef __SIM_OBJECT_HH__
#define __SIM_OBJECT_HH__
-#include <iostream>
-#include <list>
-#include <map>
#include <string>
#include <vector>
-#include "enums/MemoryMode.hh"
#include "params/SimObject.hh"
#include "sim/drain.hh"
+#include "sim/eventq.hh"
#include "sim/eventq_impl.hh"
#include "sim/serialize.hh"
-class BaseCPU;
-class Event;
+class EventManager;
class ProbeManager;
+
/**
* Abstract superclass for simulation objects. Represents things that
* correspond to physical components and can be specified via the
*/
#include "base/types.hh"
-#include "sim/sim_events.hh"
+
+class GlobalSimLoopExitEvent;
GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
extern GlobalSimLoopExitEvent *simulate_limit_event;
#include "sim/stat_register.hh"
+#include "base/statistics.hh"
+
namespace Stats
{
#ifndef __SIM_STAT_REGISTER_H__
#define __SIM_STAT_REGISTER_H__
-#include "base/statistics.hh"
-
namespace Stats
{
#include <vector>
#include "params/SubSystem.hh"
-#include "sim/power/thermal_domain.hh"
#include "sim/sim_object.hh"
class PowerModel;
#include <fcntl.h>
#include <unistd.h>
-#include <cstdio>
#include <iostream>
#include <string>
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
/// application on the host machine.
#ifdef __CYGWIN32__
-#include <sys/fcntl.h> // for O_BINARY
+#include <sys/fcntl.h>
#endif
#include <fcntl.h>
#include <cerrno>
#include <string>
-#include "base/chunk_generator.hh"
-#include "base/intmath.hh" // for RoundUp
+#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
-#include "sim/byteswap.hh"
#include "sim/emul_driver.hh"
#include "sim/process.hh"
#include "sim/syscall_debug_macros.hh"
#include "sim/syscall_emul_buf.hh"
#include "sim/syscall_return.hh"
-#include "sim/system.hh"
class SyscallDesc;
/// Target _llseek() handler.
SyscallReturn _llseekFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target munmap() handler.
SyscallReturn munmapFunc(SyscallDesc *desc, int num,
/// Target fcntl64() handler.
SyscallReturn fcntl64Func(SyscallDesc *desc, int num,
- LiveProcess *process, ThreadContext *tc);
+ LiveProcess *process, ThreadContext *tc);
/// Target setuid() handler.
SyscallReturn setuidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target getpid() handler.
SyscallReturn getpidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target getuid() handler.
SyscallReturn getuidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target getgid() handler.
SyscallReturn getgidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target getppid() handler.
SyscallReturn getppidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target geteuid() handler.
SyscallReturn geteuidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target getegid() handler.
SyscallReturn getegidFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target clone() handler.
SyscallReturn cloneFunc(SyscallDesc *desc, int num,
- LiveProcess *p, ThreadContext *tc);
+ LiveProcess *p, ThreadContext *tc);
/// Target access() handler
SyscallReturn accessFunc(SyscallDesc *desc, int num,
#ifndef __SIM_SYSCALLRETURN_HH__
#define __SIM_SYSCALLRETURN_HH__
-#include "base/types.hh"
+#include <inttypes.h>
/**
* This class represents the return value from an emulated system call,
#include "arch/isa_traits.hh"
#include "base/loader/symtab.hh"
-#include "base/misc.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "enums/MemoryMode.hh"
#include "cpu/pc_event.hh"
#endif
-class BaseCPU;
class BaseRemoteGDB;
class GDBListener;
class ObjectFile;
-class Platform;
class ThreadContext;
class System : public MemObject
#include "sim/ticked_object.hh"
+#include "params/TickedObject.hh"
+#include "sim/clocked_object.hh"
+
Ticked::Ticked(ClockedObject &object_,
Stats::Scalar *imported_num_cycles,
Event::Priority priority) :
#ifndef __SIM_TICKED_OBJECT_HH__
#define __SIM_TICKED_OBJECT_HH__
-#include "params/TickedObject.hh"
#include "sim/clocked_object.hh"
+class TickedObjectParams;
+
/** Ticked attaches gem5's event queue/scheduler to evaluate
* calls and provides a start/stop interface to ticking.
*
#include <algorithm>
#include "base/statistics.hh"
+#include "base/trace.hh"
#include "debug/VoltageDomain.hh"
#include "params/VoltageDomain.hh"
#include "sim/sim_object.hh"
#ifndef __ARCH_ALPHA_VPTR_HH__
#define __ARCH_ALPHA_VPTR_HH__
-#include "arch/isa_traits.hh"
-#include "arch/vtophys.hh"
#include "mem/fs_translating_port_proxy.hh"
class ThreadContext;