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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 1 Sep 2019 14:36:31 +0000 (15:36 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 1 Sep 2019 14:36:31 +0000 (15:36 +0100)
simple_v_extension/vblock_format/discussion.mdwn patch | blob | history

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index aea6bf4e2ab2496c1a004a20f6fc6dc99dd73472..98a1820c9c8fc74245c0995d9d8f423607604e50 100644 (file)
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -99,3 +99,4 @@ registers to be come undesirably marked as "vectors".
 # Discussion
 
 * <https://groups.google.com/forum/#!topic/comp.arch/l2nzme2sCR0>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002622.html>
http://libre-riscv.org ikiwiki