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freedreno/a5xx: fix draw packet size with index buffer
authorRob Clark <robdclark@gmail.com>
Tue, 6 Dec 2016 20:52:28 +0000 (15:52 -0500)
committerRob Clark <robdclark@gmail.com>
Tue, 6 Dec 2016 23:01:31 +0000 (18:01 -0500)
gpuaddr of idx buffer is now two dwords (64b).

Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/a5xx/fd5_draw.h patch | blob | history

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
index 677bedf4f1c3044f6dd41d6cb8da111eadda08de..8ce70d308adff55ca91c53cc307f3a1f845b6609 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
@@ -53,7 +53,7 @@ fd5_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
         */
        emit_marker5(ring, 7);
 
-       OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3);
+       OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3);
        if (vismode == USE_VISIBILITY) {
                /* leave vis mode blank for now, it will be patched up when
                 * we know if we are binning or not