sh.h (OVERRIDE_OPTIONS): Fix code that clears 'e' register class.

	* sh.h (OVERRIDE_OPTIONS): Fix code that clears 'e' register class.

	* sh.md (binary_sf_op): Use extra constant operand instead of
	negating constant operand 4.
	* sh.c (sh_expand_binop_v2sf): Supply it.

From-SVN: r63243

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 602905a9c6d9b0fd9e7803bac3bcad02ee851f56..a0cc8be3d855467af1ae34cd4ac91b62eb68c1c9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+Fri Feb 21 20:41:29 2003  J"orn Rennecke <joern.rennecke@superh.com>
+
+       * sh.h (OVERRIDE_OPTIONS): Fix code that clears 'e' register class.
+
+       * sh.md (binary_sf_op): Use extra constant operand instead of
+       negating constant operand 4.
+       * sh.c (sh_expand_binop_v2sf): Supply it.
+
 2003-02-21  Zack Weinberg  <zack@codesourcery.com>
 
        * cpphash.h (struct lexer_state): Add directive_wants_padding.

diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index b6af3def8a7ff2cc0ecafcde723c13116b671758..a0b7a92765e4f8ba2c5b79c106532ea4f39531cc 100644 (file)
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -157,7 +157,7 @@ char sh_additional_register_names[ADDREGNAMES_SIZE] \
 
 /* Provide reg_class from a letter such as appears in the machine
    description.  *: target independently reserved letter.
-   reg_class_from_letter['e'] is set to NO_REGS for TARGET_FMOVD.  */
+   reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD.  */
 
 enum reg_class reg_class_from_letter[] =
 {
@@ -4694,7 +4694,7 @@ calc_live_regs (count_ptr, live_regs_mask)
 
 /* Code to generate prologue and epilogue sequences */
 
-/* PUSHED is the number of bytes that are bing pushed on the
+/* PUSHED is the number of bytes that are being pushed on the
    stack for register saves.  Return the frame size, padded
    appropriately so that the stack stays properly aligned.  */
 static HOST_WIDE_INT
@@ -8080,11 +8080,12 @@ sh_expand_binop_v2sf (code, op0, op1, op2)
 {
   rtx sel0 = const0_rtx;
   rtx sel1 = const1_rtx;
-  rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx)) = gen_binary_sf_op;
+  rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx))
+    = gen_binary_sf_op;
   rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
 
-  emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
-  emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));
+  emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0, sel1));
+  emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1, sel0));
 }
 
 /* Return the class of registers for which a mode change from FROM to TO

diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 25406a17839ca537f785c0cea9d203d759992683..f99ed78d1ed7bd06eb73da99bab59a2cb9156ebd 100644 (file)
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -456,7 +456,7 @@ do {                                                                        \
        targetm.asm_out.unaligned_op.di = NULL;                         \
     }                                                                  \
   if (TARGET_FMOVD)                                                    \
-    reg_class_from_letter['e'] = NO_REGS;                              \
+    reg_class_from_letter['e' - 'a'] = NO_REGS;                                \
                                                                        \
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)              \
     if (! VALID_REGISTER_P (regno))                                    \

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 7c4c7ae39b5a5ae5cdf77aa602303420684e3819..e32d30a49a4d70ec076d8d93b9a4639659830381 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -8048,7 +8048,7 @@
         (vec_concat:V2SF
          (vec_select:SF
           (match_dup 0)
-          (parallel [(not:BI (match_operand 4 "const_int_operand" "n"))]))
+          (parallel [(match_operand 7 "const_int_operand" "n")]))
          (match_operator:SF 3 "binary_float_operator"
            [(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
                            (parallel [(match_operand 5
@@ -8056,11 +8056,11 @@
             (vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
                            (parallel [(match_operand 6
                                        "const_int_operand" "n")]))]))
-        (parallel [(not:BI (match_dup 4)) (match_dup 4)])))]
-  "TARGET_SHMEDIA_FPU"
+        (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
+  "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
   "#"
-  "TARGET_SHMEDIA_FPU && reload_completed"
-  [(set (match_dup 7) (match_dup 8))]
+  "&& reload_completed"
+  [(set (match_dup 8) (match_dup 9))]
   "
 {
   int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
@@ -8071,10 +8071,10 @@
                         (true_regnum (operands[2])
                          + (INTVAL (operands[6]) ^ endian)));
 
-  operands[7] = gen_rtx_REG (SFmode,
+  operands[8] = gen_rtx_REG (SFmode,
                             (true_regnum (operands[0])
                              + (INTVAL (operands[4]) ^ endian)));
-  operands[8] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
+  operands[9] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
 }"
   [(set_attr "type" "fparith_media")])