litedram: Remove remnants of riscv-inits

We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
index 8f91746560386681be7049eea007d0d596c6d522..3f95775846bc6740065f8713053df021d7ac9673 100644 (file)
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@@ -91,9 +91,6 @@ begin
             wb_ctrl_is_csr  => wb_dram_is_csr,
             wb_ctrl_is_init => wb_dram_is_init,
 
-            serial_tx  => open,
-            serial_rx  => '1',
-
             init_done  => open,
             init_error => open,
 

diff --git a/dram_tb.vhdl b/dram_tb.vhdl
index af0578e4933396103122ff619ce50b65ba4ccea2..d08544c0cb9260cfe1563100e04ed603b1658566 100644 (file)
--- a/dram_tb.vhdl
+++ b/dram_tb.vhdl
@@ -61,9 +61,6 @@ begin
             wb_ctrl_is_csr      => '0',
             wb_ctrl_is_init     => '0',
 
-            serial_tx           => open,
-            serial_rx           => '1',
-
             init_done           => open,
             init_error          => open,
 

diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index c8c2ed801050200af9f9260e9f03048f4eab8016..ee77d93c5a94cae11a9995ac34e60b319a87df15 100644 (file)
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -26,12 +26,6 @@ entity toplevel is
        uart_main_tx : out std_ulogic;
        uart_main_rx : in  std_ulogic;
 
-       -- DRAM UART signals (PMOD)
-       uart_pmod_tx    : out std_ulogic;
-       uart_pmod_rx    : in std_ulogic;
-       uart_pmod_cts_n : in std_ulogic;
-       uart_pmod_rts_n : out std_ulogic;
-
        -- LEDs
        led0_b  : out std_ulogic;
        led0_g  : out std_ulogic;
@@ -110,8 +104,6 @@ architecture behaviour of toplevel is
     constant PAYLOAD_SIZE : natural := get_payload_size;
 begin
 
-    uart_pmod_rts_n <= '0';
-
     -- Main SoC
     soc0: entity work.soc
        generic map(
@@ -232,9 +224,6 @@ begin
                wb_ctrl_is_csr  => wb_dram_is_csr,
                wb_ctrl_is_init => wb_dram_is_init,
 
-               serial_tx       => uart_pmod_tx,
-               serial_rx       => uart_pmod_rx,
-
                init_done       => dram_init_done,
                init_error      => dram_init_error,
 

diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl
index 42e6c11b8f56ce91da2950dd2a103d5b1867429d..45c2f394b7dbd0c39543adf55bb7a46b89d462a8 100644 (file)
--- a/fpga/top-nexys-video.vhdl
+++ b/fpga/top-nexys-video.vhdl
@@ -212,9 +212,6 @@ begin
                wb_ctrl_is_csr  => wb_dram_is_csr,
                wb_ctrl_is_init => wb_dram_is_init,
 
-               serial_tx       => open,
-               serial_rx       => '0',
-
                init_done       => dram_init_done,
                init_error      => dram_init_error,
 

diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl
index eb818ee02c56526c072dd3a010135d32a69e20f5..f2392f6b16238069bbe7ba37a939e3ea97cf7c0e 100644 (file)
--- a/litedram/extras/litedram-wrapper-l2.vhdl
+++ b/litedram/extras/litedram-wrapper-l2.vhdl
@@ -52,10 +52,6 @@ entity litedram_wrapper is
         wb_ctrl_is_csr  : in std_ulogic;
         wb_ctrl_is_init : in std_ulogic;
 
-        -- Init core serial debug
-        serial_tx     : out std_ulogic;
-        serial_rx     : in std_ulogic;
-
         -- Misc
         init_done     : out std_ulogic;
         init_error    : out std_ulogic;