+2019-12-13 Dennis Zhang <dennis.zhang@arm.com>
+
+ * config/aarch64/aarch64-arches.def (armv8.6-a): New.
+ * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
+ __ARM_FEATURE_MATMUL_INT8, __ARM_FEATURE_BF16_VECTOR_ARITHMETIC and
+ __ARM_FEATURE_BF16_SCALAR_ARITHMETIC when enabled.
+ * config/aarch64/aarch64-option-extensions.def (i8mm, bf16): New.
+ (fp): Disabling fp also disables i8mm and bf16.
+ (simd): Disabling simd also disables i8mm.
+ * config/aarch64/aarch64.h (AARCH64_FL_V8_6): New macro.
+ (AARCH64_FL_I8MM, AARCH64_FL_BF16, AARCH64_FL_FOR_ARCH8_6): Likewise.
+ (AARCH64_ISA_V8_6, AARCH64_ISA_I8MM, AARCH64_ISA_BF16): Likewise.
+ (TARGET_I8MM, TARGET_BF16_FP, TARGET_BF16_SIMD): Likewise.
+ * doc/invoke.texi (armv8.6-a, i8mm, bf16): Document new options
+ and add a new table to list permissible values for ARCH.
+
2019-12-13 Jakub Jelinek <jakub@redhat.com>
PR target/92908
AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3)
AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4)
AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5)
+AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6)
#undef AARCH64_ARCH
aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
+ aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
+ aarch64_def_or_undef (TARGET_BF16_SIMD,
+ "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
+ aarch64_def_or_undef (TARGET_BF16_FP,
+ "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile);
+
/* Not for ACLE, but required to keep "float.h" correct if we switch
target between implementations that do or do not support ARMv8.2-A
16-bit floating-point extensions. */
/* Enabling "fp" just enables "fp".
Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
- "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
- "sve2-bitperm". */
+ "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
+ "sve2-bitperm", "i8mm" and "bf16". */
AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
- AARCH64_FL_SVE2_BITPERM, false, "fp")
+ AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
+ AARCH64_FL_BF16, false, "fp")
/* Enabling "simd" also enables "fp".
Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
- "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
- "sve2-bitperm". */
+ "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
+ "sve2-bitperm", and "i8mm". */
AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
- AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
+ AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
+ AARCH64_FL_I8MM, false, \
"asimd")
/* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
/* Enabling or disabling "tme" only changes "tme". */
AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
+/* Enabling "i8mm" also enables "simd" and "fp".
+ Disabling "i8mm" only disables "i8mm". */
+AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, \
+ AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "i8mm")
+
+/* Enabling "bf16" also enables "simd" and "fp".
+ Disabling "bf16" only disables "bf16". */
+AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \
+ AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "bf16")
+
#undef AARCH64_OPT_EXTENSION
/* Transactional Memory Extension. */
#define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */
+/* Armv8.6-A architecture extensions. */
+#define AARCH64_FL_V8_6 (1ULL << 34)
+
+/* 8-bit Integer Matrix Multiply (I8MM) extensions. */
+#define AARCH64_FL_I8MM (1ULL << 35)
+
+/* Brain half-precision floating-point (BFloat16) Extension. */
+#define AARCH64_FL_BF16 (1ULL << 36)
+
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
#define AARCH64_FL_FOR_ARCH8_5 \
(AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5 \
| AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES)
+#define AARCH64_FL_FOR_ARCH8_6 \
+ (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \
+ | AARCH64_FL_I8MM | AARCH64_FL_BF16)
/* Macros to test ISA flags. */
#define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5)
#define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)
#define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG)
+#define AARCH64_ISA_V8_6 (aarch64_isa_flags & AARCH64_FL_V8_6)
+#define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM)
+#define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
/* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */
#define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG)
+/* I8MM instructions are enabled through +i8mm. */
+#define TARGET_I8MM (AARCH64_ISA_I8MM)
+
+/* BF16 instructions are enabled through +bf16. */
+#define TARGET_BF16_FP (AARCH64_ISA_BF16)
+#define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
+
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
more feature modifiers. This option has the form
@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
-The permissible values for @var{arch} are @samp{armv8-a},
-@samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a}, @samp{armv8.4-a},
-@samp{armv8.5-a} or @var{native}.
-
-The value @samp{armv8.5-a} implies @samp{armv8.4-a} and enables compiler
-support for the ARMv8.5-A architecture extensions.
-
-The value @samp{armv8.4-a} implies @samp{armv8.3-a} and enables compiler
-support for the ARMv8.4-A architecture extensions.
-
-The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler
-support for the ARMv8.3-A architecture extensions.
-
-The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
-support for the ARMv8.2-A architecture extensions.
-
-The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
-support for the ARMv8.1-A architecture extension. In particular, it
-enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features.
+The table below summarizes the permissible values for @var{arch}
+and the features that they enable by default:
+
+@multitable @columnfractions 0.20 0.20 0.60
+@headitem @var{arch} value @tab Architecture @tab Includes by default
+@item @samp{armv8-a} @tab Armv8-A @tab @samp{+fp}, @samp{+simd}
+@item @samp{armv8.1-a} @tab Armv8.1-A @tab @samp{armv8-a}, @samp{+crc}, @samp{+lse}, @samp{+rdma}
+@item @samp{armv8.2-a} @tab Armv8.2-A @tab @samp{armv8.1-a}
+@item @samp{armv8.3-a} @tab Armv8.3-A @tab @samp{armv8.2-a}
+@item @samp{armv8.4-a} @tab Armv8.4-A @tab @samp{armv8.3-a}, @samp{+fp16fml}, @samp{+dotprod}
+@item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres}
+@item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm}
+@end multitable
The value @samp{native} is available on native AArch64 GNU/Linux and
causes the compiler to pick the architecture of the host system. This
Enable the Armv8-a Execution and Data Prediction Restriction instructions.
This option is only to enable the extension at the assembler level and does
not affect code generation. This option is enabled by default for
+@option{-march=armv8.5-a}.
@item sve2
Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
instructions.
Enable SVE2 aes instructions. This also enables SVE2 instructions.
@item sve2-sha3
Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
-@option{-march=armv8.5-a}.
@item tme
Enable the Transactional Memory Extension.
+@item i8mm
+Enable 8-bit Integer Matrix Multiply instructions. This also enables
+Advanced SIMD and floating-point instructions. This option is enabled by
+default for @option{-march=armv8.6-a}. Use of this option with architectures
+prior to Armv8.2-A is not supported.
+@item bf16
+Enable brain half-precision floating-point instructions. This also enables
+Advanced SIMD and floating-point instructions. This option is enabled by
+default for @option{-march=armv8.6-a}. Use of this option with architectures
+prior to Armv8.2-A is not supported.
@end table
+2019-12-13 Dennis Zhang <dennis.zhang@arm.com>
+
+ * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add tests for i8mm
+ and bf16 features.
+
2019-12-13 Jakub Jelinek <jakub@redhat.com>
PR target/92908
/* { dg-do compile } */
/* { dg-options "-O2" } */
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8-a")
+
#pragma GCC push_options
#pragma GCC target ("arch=armv8-a+tme")
#ifndef __ARM_FEATURE_TME
#error "__ARM_FEATURE_TME is defined but should not be!"
#endif
+/* Test Armv8.6-A features. */
+
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a")
+#ifndef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+i8mm")
+#ifndef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nosimd")
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nofp")
+#ifdef __ARM_FEATURE_MATMUL_INT8
+#error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is defined but should not be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+bf16")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifndef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+bf16+nosimd")
+#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is not defined but should be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv8.6-a+nofp")
+#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC is defined but should not be!"
+#endif
+#ifdef __ARM_FEATURE_BF16_VECTOR_ARITHMETIC
+#error "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC is defined but should not be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC pop_options
+
int
foo (int a)
{
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