genlib/cdc/MultiReg: output clock domain defaults to sys

diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py
index a7c2dd85331754c6e44f5e6438f33b9c13fcec4e..7aff864d5fa354b1c1f476cb2f75c4784db47560 100644 (file)
--- a/migen/genlib/cdc.py
+++ b/migen/genlib/cdc.py
@@ -23,7 +23,7 @@ class MultiRegImpl:
                return Fragment(comb, {self.odomain: o_sync})
 
 class MultiReg(Special):
-       def __init__(self, i, o, odomain, n=2):
+       def __init__(self, i, o, odomain="sys", n=2):
                Special.__init__(self)
                self.i = i
                self.o = o