Make CPU models signal to update the snoop ranges

--HG--
extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 91e073cf0d022b764ff51dc9788481c3dc6d59c7..180f41541531a6a178891a71beff0724e9d2c07c 100644 (file)
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -81,8 +81,13 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
 void
 MemTest::CpuPort::recvStatusChange(Status status)
 {
-    if (status == RangeChange)
+    if (status == RangeChange) {
+        if (!snoopRangeSent) {
+            snoopRangeSent = true;
+            sendStatusChange(Port::RangeChange);
+        }
         return;
+    }
 
     panic("MemTest doesn't expect recvStatusChange callback!");
 }
@@ -145,6 +150,9 @@ MemTest::MemTest(const string &name,
     //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
     curTick = 0;
 
+    cachePort.snoopRangeSent = false;
+    funcPort.snoopRangeSent = true;
+
     // Needs to be masked off once we know the block size.
     traceBlockAddr = _traceAddr;
     baseAddr1 = 0x100000;

diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 2694efd39d00ae92aa54811972dd7decb376515f..7bf34d827281c5b82f78109d41162f2708df9de6 100644 (file)
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -100,6 +100,8 @@ class MemTest : public MemObject
             : Port(_name, _memtest), memtest(_memtest)
         { }
 
+        bool snoopRangeSent;
+
       protected:
 
         virtual bool recvTiming(PacketPtr pkt);
@@ -120,6 +122,8 @@ class MemTest : public MemObject
     CpuPort cachePort;
     CpuPort funcPort;
 
+    bool snoopRangeSent;
+
     class MemTestSenderState : public Packet::SenderState
     {
       public:

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index cc9a8abf5567ceb41d7b5120cc1b6c74512f6b08..04016347a4ef316c3f35cb0d4cf5475805b455f4 100644 (file)
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,6 +83,8 @@ class DefaultFetch
             : Port(_fetch->name() + "-iport"), fetch(_fetch)
         { }
 
+        bool snoopRangeSent;
+
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 25faa407e46c75baeaea4629196f741b61af06c9..63d22b2932dca2ab86a81c3f7ce6a1979783f290 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -70,8 +70,13 @@ template<class Impl>
 void
 DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
 {
-    if (status == RangeChange)
+    if (status == RangeChange) {
+        if (!snoopRangeSent) {
+            snoopRangeSent = true;
+            sendStatusChange(Port::RangeChange);
+        }
         return;
+    }
 
     panic("DefaultFetch doesn't expect recvStatusChange callback!");
 }
@@ -287,6 +292,8 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
     // Name is finally available, so create the port.
     icachePort = new IcachePort(this);
 
+    icachePort->snoopRangeSent = false;
+
 #if USE_CHECKER
     if (cpu->checker) {
         cpu->checker->setIcachePort(icachePort);

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 6b12d75b4f29474acca1bf738b5117215e9bdfa6..7559a36d57c14b3eb378c90e220ec49d81883fe3 100644 (file)
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -298,6 +298,8 @@ class LSQ {
             : lsq(_lsq)
         { }
 
+        bool snoopRangeSent;
+
       protected:
         /** Atomic version of receive.  Panics. */
         virtual Tick recvAtomic(PacketPtr pkt);

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5e7945c1ccbe6f31d3717c8e764d5618fadfb2e3..6758e51c89dc97a4878fdacced42c3aec5cb38d4 100644 (file)
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -53,9 +53,13 @@ template <class Impl>
 void
 LSQ<Impl>::DcachePort::recvStatusChange(Status status)
 {
-    if (status == RangeChange)
+    if (status == RangeChange) {
+        if (!snoopRangeSent) {
+            snoopRangeSent = true;
+            sendStatusChange(Port::RangeChange);
+        }
         return;
-
+    }
     panic("O3CPU doesn't expect recvStatusChange callback!");
 }
 
@@ -97,6 +101,8 @@ LSQ<Impl>::LSQ(Params *params)
 {
     DPRINTF(LSQ, "Creating LSQ object.\n");
 
+    dcachePort.snoopRangeSent = false;
+
     //**********************************************/
     //************ Handle SMT Parameters ***********/
     //**********************************************/

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 58dc1fe5f6b09accd89efb43294182a03aa55a65..9a1f831cd08901bd0ff57b5b6f0367ca02aa7466 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -107,8 +107,13 @@ AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
 void
 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
 {
-    if (status == RangeChange)
+    if (status == RangeChange) {
+        if (!snoopRangeSent) {
+            snoopRangeSent = true;
+            sendStatusChange(Port::RangeChange);
+        }
         return;
+    }
 
     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 }
@@ -127,6 +132,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 {
     _status = Idle;
 
+    icachePort.snoopRangeSent = false;
+    dcachePort.snoopRangeSent = false;
+
     ifetch_req = new Request();
     ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 166a181275f68bdd9a1553509217f438fd0cd490..0df6fe079df7d68274517968bfcfedf8568f905e 100644 (file)
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -90,6 +90,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
             : Port(_name, _cpu), cpu(_cpu)
         { }
 
+        bool snoopRangeSent;
+
       protected:
 
         virtual bool recvTiming(PacketPtr pkt);

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index db2c940c0940feada548e3e56950fa6573fe5a85..1ea2df894c2efb07b9b13082c9a3144bcff501c0 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -82,8 +82,13 @@ TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
 void
 TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
 {
-    if (status == RangeChange)
+    if (status == RangeChange) {
+        if (!snoopRangeSent) {
+            snoopRangeSent = true;
+            sendStatusChange(Port::RangeChange);
+        }
         return;
+    }
 
     panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
 }
@@ -101,6 +106,10 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
       cpu_id(p->cpu_id)
 {
     _status = Idle;
+
+    icachePort.snoopRangeSent = false;
+    dcachePort.snoopRangeSent = false;
+
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
     fetchEvent = NULL;

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 408fa315e04c1e1586eb77269edf112526da8ed7..fe5d036662cc4f459efa44d0e21f1669de0bc568 100644 (file)
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -82,6 +82,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
             : Port(_name, _cpu), cpu(_cpu), lat(_lat)
         { }
 
+        bool snoopRangeSent;
+
       protected:
 
         virtual Tick recvAtomic(PacketPtr pkt);
@@ -166,8 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
     PacketPtr ifetch_pkt;
     PacketPtr dcache_pkt;
 
-
-
     int cpu_id;
     Tick previousTick;