/* The hash table of address types. */
static struct hash_control *arc_addrtype_hash;
+#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
+ E_ARC_MACH_ARC600, EXTRA}
+#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
+ E_ARC_MACH_ARC700, EXTRA}
+#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
+ EF_ARC_CPU_ARCV2EM, EXTRA}
+#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
+ EF_ARC_CPU_ARCV2HS, EXTRA}
+
/* A table of CPU names and opcode sets. */
static const struct cpu_type
{
}
cpu_types[] =
{
- { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
- E_ARC_MACH_ARC600, 0x00},
- { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
- E_ARC_MACH_ARC700, 0x00},
- { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
- E_ARC_MACH_ARC700, ARC_NPS400},
- { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
- EF_ARC_CPU_ARCV2EM, 0x00},
- { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
- EF_ARC_CPU_ARCV2HS, ARC_CD},
+ ARC_CPU_TYPE_A7xx (arc700, 0x00),
+ ARC_CPU_TYPE_A7xx (nps400, ARC_NPS400),
+
+ ARC_CPU_TYPE_AV2EM (arcem, 0x00),
+ ARC_CPU_TYPE_AV2EM (em, 0x00),
+ ARC_CPU_TYPE_AV2EM (em4, ARC_CD),
+ ARC_CPU_TYPE_AV2EM (em4_dmips, ARC_CD),
+ ARC_CPU_TYPE_AV2EM (em4_fpus, ARC_CD),
+ ARC_CPU_TYPE_AV2EM (em4_fpuda, ARC_CD | ARC_FPUDA),
+ ARC_CPU_TYPE_AV2EM (quarkse_em, ARC_CD | ARC_SPFP | ARC_DPFP),
+
+ ARC_CPU_TYPE_AV2HS (archs, ARC_CD),
+ ARC_CPU_TYPE_AV2HS (hs, ARC_CD),
+ ARC_CPU_TYPE_AV2HS (hs34, ARC_CD),
+ ARC_CPU_TYPE_AV2HS (hs38, ARC_CD),
+ ARC_CPU_TYPE_AV2HS (hs38_linux, ARC_CD),
+
+ ARC_CPU_TYPE_A6xx (arc600, 0x00),
+ ARC_CPU_TYPE_A6xx (arc600_norm, 0x00),
+ ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00),
+ ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00),
+ ARC_CPU_TYPE_A6xx (arc601, 0x00),
+ ARC_CPU_TYPE_A6xx (arc601_norm, 0x00),
+ ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00),
+ ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00),
{ 0, 0, 0, 0, 0 }
};
{ ARC_FPUDA, ARC_OPCODE_ARCv2EM, "double assist FP" }
};
+/* Command line given features. */
+static unsigned cl_features = 0;
+
/* Used by the arc_reloc_op table. Order is important. */
#define O_gotoff O_md1 /* @gotoff relocation. */
#define O_gotpc O_md2 /* @gotpc relocation. */
/* Initialise static global data about selected machine type. */
selected_cpu.flags = cpu_types[i].flags;
selected_cpu.name = cpu_types[i].name;
- selected_cpu.features |= cpu_types[i].features;
+ selected_cpu.features = cpu_types[i].features | cl_features;
selected_cpu.mach = cpu_types[i].mach;
cpu_flags = cpu_types[i].eflags;
break;
c = get_symbol_name (&cpu);
+ cpu_name = cpu;
if ((!strcmp ("ARC600", cpu))
|| (!strcmp ("ARC601", cpu))
|| (!strcmp ("A6", cpu)))
cpu_name = "archs";
else if (!strcmp ("NPS400", cpu))
cpu_name = "nps400";
- else
- cpu_name = NULL;
- if (cpu_name != NULL)
- arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
- else
- as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu);
+ arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
as_fatal (_("could not set architecture and machine"));
case OPTION_CD:
selected_cpu.features |= ARC_CD;
+ cl_features |= ARC_CD;
arc_check_feature ();
break;
case OPTION_NPS400:
selected_cpu.features |= ARC_NPS400;
+ cl_features |= ARC_NPS400;
arc_check_feature ();
break;
case OPTION_SPFP:
selected_cpu.features |= ARC_SPFP;
+ cl_features |= ARC_SPFP;
arc_check_feature ();
break;
case OPTION_DPFP:
selected_cpu.features |= ARC_DPFP;
+ cl_features |= ARC_DPFP;
arc_check_feature ();
break;
case OPTION_FPUDA:
selected_cpu.features |= ARC_FPUDA;
+ cl_features |= ARC_FPUDA;
arc_check_feature ();
break;
return 1;
}
+/* Display the list of cpu names for use in the help text. */
+
+static void
+arc_show_cpu_list (FILE *stream)
+{
+ int i, offset;
+ static const char *spaces = " ";
+
+ fprintf (stream, "%s", spaces);
+ offset = strlen (spaces);
+ for (i = 0; cpu_types[i].name != NULL; ++i)
+ {
+ bfd_boolean last = (cpu_types[i + 1].name == NULL);
+
+ /* If displaying the new cpu name string, and the ', ' (for all
+ but the last one) will take us past a target width of 80
+ characters, then it's time for a new line. */
+ if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
+ {
+ fprintf (stream, "\n%s", spaces);
+ offset = strlen (spaces);
+ }
+
+ fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
+ offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
+ }
+}
+
void
md_show_usage (FILE *stream)
{
fprintf (stream, _("ARC-specific assembler options:\n"));
- fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name> "
- "(default: %s)\n", TARGET_WITH_CPU);
- fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n");
+ fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
+ " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
+ arc_show_cpu_list (stream);
+ fprintf (stream, "\n");
fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
- fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n");
- fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n");
+ fprintf (stream, " -mspfp\t\t enable single-precision floating point"
+ " instructions\n");
+ fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
+ " instructions\n");
fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
"point\n\t\t\t instructions for ARC EM\n");
@item arc600
Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
+@item arc600_norm
+Assemble for ARC 600 with norm instructions.
+
+@item arc600_mul64
+Assemble for ARC 600 with mul64 instructions.
+
+@item arc600_mul32x16
+Assemble for ARC 600 with mul32x16 instructions.
+
@item arc601
@cindex @code{mARC601} command line option, ARC
Assemble for ARC 601. Alias: @code{-mARC601}.
+@item arc601_norm
+Assemble for ARC 601 with norm instructions.
+
+@item arc601_mul64
+Assemble for ARC 601 with mul64 instructions.
+
+@item arc601_mul32x16
+Assemble for ARC 601 with mul32x16 instructions.
+
@item arc700
@cindex @code{mA7} command line option, ARC
@cindex @code{mARC700} command line option, ARC
@cindex @code{mEM} command line option, ARC
Assemble for ARC EM. Aliases: @code{-mEM}
+@item em
+Assemble for ARC EM, identical as arcem variant.
+
+@item em4
+Assemble for ARC EM with code-density instructions.
+
+@item em4_dmips
+Assemble for ARC EM with code-density instructions.
+
+@item em4_fpus
+Assemble for ARC EM with code-density instructions.
+
+@item em4_fpuda
+Assemble for ARC EM with code-density, and double-precision assist
+instructions.
+
+@item quarkse_em
+Assemble for QuarkSE-EM cpu.
+
@item archs
@cindex @code{mHS} command line option, ARC
Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
+@item hs
+Assemble for ARC HS.
+
+@item hs34
+Assemble for ARC HS34.
+
+@item hs38
+Assemble for ARC HS38.
+
+@item hs38_linux
+Assemble for ARC HS38 with floating point support on.
+
@item nps400
@cindex @code{mnps400} command line option, ARC
Assemble for ARC 700 with NPS-400 extended instructions.
@item ARC600
Assemble for the ARC600 instruction set.
+@item arc600_norm
+Assemble for ARC 600 with norm instructions.
+
+@item arc600_mul64
+Assemble for ARC 600 with mul64 instructions.
+
+@item arc600_mul32x16
+Assemble for ARC 600 with mul32x16 instructions.
+
+@item arc601
+Assemble for ARC 601 instruction set.
+
+@item arc601_norm
+Assemble for ARC 601 with norm instructions.
+
+@item arc601_mul64
+Assemble for ARC 601 with mul64 instructions.
+
+@item arc601_mul32x16
+Assemble for ARC 601 with mul32x16 instructions.
+
@item ARC700
Assemble for the ARC700 instruction set.
@item EM
Assemble for the ARC EM instruction set.
+@item arcem
+Assemble for ARC EM instruction set
+
+@item em4
+Assemble for ARC EM with code-density instructions.
+
+@item em4_dmips
+Assemble for ARC EM with code-density instructions.
+
+@item em4_fpus
+Assemble for ARC EM with code-density instructions.
+
+@item em4_fpuda
+Assemble for ARC EM with code-density, and double-precision assist
+instructions.
+
+@item quarkse_em
+Assemble for QuarkSE-EM instruction set.
+
@item HS
Assemble for the ARC HS instruction set.
+@item archs
+Assemble for ARC HS instruction set.
+
+@item hs
+Assemble for ARC HS instruction set.
+
+@item hs34
+Assemble for ARC HS34 instruction set.
+
+@item hs38
+Assemble for ARC HS38 instruction set.
+
+@item hs38_linux
+Assemble for ARC HS38 with floating point support on.
+
@end table
Note: the @code{.cpu} directive overrides the command line option
projects / binutils-gdb.git / commitdiff