add vcd generator

diff --git a/migScope/tools/conv.py b/migScope/tools/conv.py
new file mode 100644 (file)
index 0000000..66f7551
--- /dev/null
+++ b/migScope/tools/conv.py
@@ -0,0 +1,13 @@
+import datetime
+
+def dec2bin(d,nb=0):
+       if d=="x":
+               return "x"*nb
+       elif d==0:
+               b="0"
+       else:
+               b=""
+               while d!=0:
+                       b="01"[d&1]+b
+                       d=d>>1
+       return b.zfill(nb)
\ No newline at end of file

diff --git a/migScope/tools/vcd.py b/migScope/tools/vcd.py
new file mode 100644 (file)
index 0000000..5a36be4
--- /dev/null
+++ b/migScope/tools/vcd.py
@@ -0,0 +1,169 @@
+import datetime
+
+from conv import *
+
+class Var:
+       def __init__(self,type , width , name, values=[], default="x"):
+               self.type = type
+               self.width = width
+               self.name = name
+               self.val = default
+               self.values = values
+               self.vcd_id = None
+               
+       def set_vcd_id(self, s):
+               self.vcd_id = s
+       
+       def __len__(self):
+               return len(self.values)
+
+       def change(self, cnt):
+               r = ""
+               try : 
+                       if self.values[cnt+1] != self.val:
+                               r += "b"
+                               r += dec2bin(self.values[cnt+1],self.width)
+                               r += " "
+                               r += self.vcd_id
+                               r += "\n"
+                               return r
+               except :
+                       return r
+               return r
+       
+               
+class Vcd:
+       def __init__(self,timescale = "1ps", comment = ""):
+               self.timescale = timescale
+               self.comment = comment
+               self.vars = []
+               self.vcd_id = "!"
+               self.cnt = -1
+               
+       def add(self, var):
+               var.set_vcd_id(self.vcd_id)
+               self.vcd_id = chr(ord(self.vcd_id)+1)
+               self.vars.append(var)
+       
+       def __len__(self):
+               l = 0
+               for var in self.vars:
+                       l = max(len(var),l)
+               return l
+       
+       def change(self):
+               r = ""
+               c = ""
+               for var in self.vars:
+                       c += var.change(self.cnt)
+               if c != "":
+                       r += "#"
+                       r += str(self.cnt+1)
+                       r += "\n"
+                       r += c
+               return r
+
+       
+       def p_date(self):
+               now = datetime.datetime.now()
+               r = "$date\n"
+               r += "\t"
+               r += now.strftime("%Y-%m-%d %H:%M")
+               r += "\n"
+               r += "$end\n"
+               return r
+               
+       def p_version(self):
+               r  = "$version\n"
+               r += "\tmiscope VCD dump\n"
+               r += "$end\n"
+               return r
+               
+       def p_comment(self):
+               r  = "$comment\n"
+               r += self.comment
+               r += "\n$end\n"
+               return r
+               
+       def p_timescale(self):
+               r  = "$timescale "
+               r += self.timescale
+               r += " $end\n"
+               return r
+               
+       def p_scope(self):
+               r  = "$scope "
+               r += self.timescale
+               r += " $end\n"
+               return r
+       def  p_vars(self):
+               r = ""
+               for var in self.vars:
+                       r += "$var "
+                       r += var.type
+                       r += " "
+                       r += str(var.width)
+                       r += " "
+                       r += var.vcd_id
+                       r += " "
+                       r += var.name
+                       r += " $end\n"
+               return r
+               
+       def p_unscope(self):
+               r  = "$unscope "
+               r += " $end\n"
+               return r
+       
+       def p_enddefinitions(self):
+               r  = "$enddefinitions "
+               r += " $end\n"
+               return r
+       
+       def p_dumpvars(self):
+               r  = "$dumpvars\n"
+               for var in self.vars:
+                       r += "b"
+                       r += dec2bin(var.val, var.width)
+                       r += " "
+                       r += var.vcd_id
+                       r+= "\n"
+               r += "$end\n"
+               return r
+               
+       def p_valuechange(self):
+               r = ""
+               for i in range(len(self)):
+                       r += self.change()
+                       self.cnt += 1
+               return r
+               
+
+       def __repr__(self):
+               r = ""
+               r += self.p_date()
+               r += self.p_version()
+               r += self.p_comment()
+               r += self.p_timescale()
+               r += self.p_scope()
+               r += self.p_vars()
+               r += self.p_unscope()
+               r += self.p_enddefinitions()
+               r += self.p_dumpvars()
+               r += self.p_valuechange()
+               return r
+       
+
+def main():
+       myvcd = Vcd()
+       myvcd.add(Var("wire",1,"foo1",[0,1,0,1,0,1]))
+       myvcd.add(Var("wire",2,"foo2",[1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
+       myvcd.add(Var("wire",3,"foo3"))
+       myvcd.add(Var("wire",4,"foo4"))
+       ramp = [i%128 for i in range(1024)]
+       myvcd.add(Var("wire",16,"sinus",ramp))
+       print(myvcd)
+       
+if __name__ == '__main__':
+  main()
+

diff --git a/sim/tb_spi2Csr.py b/sim/tb_spi2Csr.py
index 781c657e4eb6a46e78742a4d9ce65369a1281430..cee3925c49cd093f416d1c1c8efd495164781272 100644 (file)
--- a/sim/tb_spi2Csr.py
+++ b/sim/tb_spi2Csr.py
@@ -13,6 +13,7 @@ import spi2Csr
 
 def get_bit(dat, bit):
        return int(dat & (1<<bit) != 0)
+
 def set_bit(dat, bit):
        return dat | (1<<bit)   
 
@@ -57,8 +58,8 @@ class SpiMaster(PureSimulable):
                                if self.transaction is not None:
                                        self.transaction_cnt = 0
                                        self.r_dat = 0
-                                       print(self.transaction)                         
-                       elif isinstance(self.transaction, TWrite):      
+                                       print(self.transaction)
+                       elif isinstance(self.transaction, TWrite):
                        
                                        # Clk
                                        if (int(self.transaction_cnt/(self.clk_ratio/2)))%2:
@@ -76,9 +77,9 @@ class SpiMaster(PureSimulable):
                                                s.wr(self.spi.spi_mosi, data)
                                        # Mosi Data
                                        elif self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt < (a_w + d_w)*self.clk_ratio:
-                                               bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)                                       
+                                               bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
                                                data = get_bit(self.transaction.data,bit)
-                                               s.wr(self.spi.spi_mosi, data)                                           
+                                               s.wr(self.spi.spi_mosi, data)
                                        else:
                                                s.wr(self.spi.spi_mosi, 0)
 
@@ -109,7 +110,7 @@ class SpiMaster(PureSimulable):
                                                        data = 0
                                                else:
                                                        data = get_bit(self.transaction.address, bit)
-                                               s.wr(self.spi.spi_mosi, data)                                   
+                                               s.wr(self.spi.spi_mosi, data)
                                        else:
                                                s.wr(self.spi.spi_mosi, 0)
                                        
@@ -117,7 +118,7 @@ class SpiMaster(PureSimulable):
                                        if self.transaction_cnt >= a_w*self.clk_ratio and self.transaction_cnt%self.clk_ratio==self.clk_ratio/2:
                                                bit = d_w-1-int((self.transaction_cnt-a_w*self.clk_ratio)/self.clk_ratio)
                                                if s.rd(self.spi.spi_miso):
-                                                       self.r_dat = set_bit(self.r_dat, bit)                                                   
+                                                       self.r_dat = set_bit(self.r_dat, bit)
 
                                        # Cs_n
                                        if self.transaction_cnt < (a_w + d_w)*self.clk_ratio: