uart: rename wishbone to bridge

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 99b117c8645158a16477146c8d62966c0a35c980..14c9cbfac1ab003644283bda6dc2ea5c77ed4808 100644 (file)
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index c4c9e550714b565f3ebbcfc328450c550ac01cfc..90f3ec889f1923682f0b23addd6456ce45a44daf 100644 (file)
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -7,7 +7,7 @@ from migen.genlib.misc import timeline
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint

diff --git a/misoclib/com/uart/bridge.py b/misoclib/com/uart/bridge.py
new file mode 100644 (file)
index 0000000..fc0d292
--- /dev/null
+++ b/misoclib/com/uart/bridge.py
@@ -0,0 +1,9 @@
+from migen.fhdl.std import *
+
+from misoclib.tools.wishbone import WishboneStreamingBridge
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+class UARTWishboneBridge(WishboneStreamingBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
+        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

diff --git a/misoclib/com/uart/wishbone.py b/misoclib/com/uart/wishbone.py
deleted file mode 100644 (file)
index fc0d292..0000000
--- a/misoclib/com/uart/wishbone.py
+++ /dev/null
@@ -1,9 +0,0 @@
-from migen.fhdl.std import *
-
-from misoclib.tools.wishbone import WishboneStreamingBridge
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-
-class UARTWishboneBridge(WishboneStreamingBridge):
-    def __init__(self, pads, clk_freq, baudrate=115200):
-        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
-        WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
index ce7d53a102cb390d3fe19bdf6f9a4e330d13aa07..60f7fcd96bdc7157ce4f26ff3c79345307b27df9 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/bist.py
+++ b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -9,7 +9,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index 26853f7e9b3f371e24524162e77af6ff4793fb2f..f9246053becf43cfcfe48bfd8cd2f31110fe572f 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -7,7 +7,7 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {