Comment out code that messed up SMT (but will be needed eventually).

src/cpu/o3/cpu.cc:
    Comment out reseting CPU structures for now.  This can be updated to work in the future.

--HG--
extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index d1d25dd7feb43ae5ce9cc62dfa1090133d9e67e0..4c9a8e91f5e8c4f49cf358aea31adc1604071468 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -701,10 +701,17 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
     assert(iew.ldstQueue.getCount(tid) == 0);
 
     // Reset ROB/IQ/LSQ Entries
+
+    // Commented out for now.  This should be possible to do by
+    // telling all the pipeline stages to drain first, and then
+    // checking until the drain completes.  Once the pipeline is
+    // drained, call resetEntries(). - 10-09-06 ktlim
+/*
     if (activeThreads.size() >= 1) {
         commit.rob->resetEntries();
         iew.resetEntries();
     }
+*/
 }