litesata: pep8 (E222)

diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
index 171be40761d13c18edc708a86e37e3361e9a2b2a..2a8b5829dc696b7ed65e9f2aae196c4ec8a43f7e 100755 (executable)
--- a/misoclib/mem/litesata/example_designs/make.py
+++ b/misoclib/mem/litesata/example_designs/make.py
@@ -72,7 +72,7 @@ if __name__ == "__main__":
     platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
     platform = platform_module.Platform(**platform_kwargs)
 
-    build_name = top_class.__name__.lower() +  "-" + platform_name
+    build_name = top_class.__name__.lower() + "-" + platform_name
     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
     soc = top_class(platform, **top_kwargs)
     soc.finalize()

diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py
index 643dfac3dc7897bed3ae5f5bda1eef3bacf71de0..50663442766182331de66f6ca088724628885fd0 100644 (file)
--- a/misoclib/mem/litesata/test/hdd.py
+++ b/misoclib/mem/litesata/test/hdd.py
@@ -433,7 +433,7 @@ class CommandLayer(Module):
         resp = None
         if isinstance(fis, FIS_REG_H2D):
             if fis.command == regs["WRITE_DMA_EXT"]:
-                resp =  self.hdd.write_dma_callback(fis)
+                resp = self.hdd.write_dma_callback(fis)
             elif fis.command == regs["READ_DMA_EXT"]:
                 resp = self.hdd.read_dma_callback(fis)
         elif isinstance(fis, FIS_DATA):