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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index cc7f4098f1d0db5d318fa52622df56fae98b9142..32a3504fc9218b017b26a39da13e6f1955dc8e0a 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -500,6 +500,23 @@ concept needs no branches, no complex Register Hazard
 Management because it is down to the programmer (or, the compiler),
 to ensure data overlaps do not occur.
 
+Zero-Overhead Loop Control takes this basic "single loop" concept
+way further: both nested loops and conditional exit are included,
+but also arbitrary control-jumping from the current inner loop
+out to an entirely different loop, all based on conditions determined
+dynamically at runtime.
+
+Even when deployed on as basic a CPU as a single-issue in-order RISC
+core, the performance and power-savings were astonishing: between 20
+and **80** reduction in algorithm completion times were achieved compared
+to a more traditional branch-speculative in-order RISC CPU.  MPEG
+Decode, the target algorithm specifically picked by the researcher
+due to its high complexity with 6-deep nested loops and conditional
+execution that frequently jumped in and out of at least 2 loops,
+came out with an astonishing 43% improvement in completion time. 43%
+less instructions executed is an almost unheard-of level of optimisation:
+most ISA designers are elated if they can achieve 5 to 10%.
+
 **OpenCAPI and Extra-V**
 
 **Snitch**