arch-power: Fix load-store instructions for timing cpu

To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.

The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
  * Load Byte and Zero with Update (lbzu)
  * Load Halfword and Zero with Update (lhzu)
  * Load Halfword Algebraic with Update (lhau)
  * Load Word and Zero with Update (lwzu)
  * Load Doubleword with Update (ldu)
  * Load Floating Single with Update (lfsu)
  * Load Floating Double with Update (lfdu)
  * Load Byte and Zero with Update Indexed (lbzux)
  * Load Halfword and Zero with Update Indexed (lhzux)
  * Load Halfword Algebraic with Update Indexed (lhaux)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word Algebraic with Update Indexed (lwaux)
  * Load Doubleword with Update Indexed (ldux)
  * Load Floating Single with Update Indexed (lfsux)
  * Load Floating Double with Update Indexed (lfdux)
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Word And Reserve Indexed (lwarx)
  * Load Doubleword And Reserve Indexed (ldarx)
  * Store Byte with Update (stbu)
  * Store Halfword with Update (sthu)
  * Store Word with Update (stwu)
  * Store Doubleword with Update (stdu)
  * Store Byte with Update Indexed (stbux)
  * Store Halfword with Update Indexed (sthux)
  * Store Word with Update Indexed (stwux)
  * Store Doubleword with Update Indexed (stdux)
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Word Conditional Indexed (stwcx.)
  * Store Doubleword Conditional Indexed (stdcx.)
  * Store Floating Single with Update (stfsu)
  * Store Floating Double with Update (stdsu)
  * Store Floating Single with Update Indexed (stfsux)
  * Store Floating Double with Update Indexed (stfdux)

Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index aeee29a034289071de4841612ac52a78b2f79d17..1db81599b9d6ffc75455b9db6964ac103b3b8450 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -313,17 +313,21 @@ decode PO default Unknown::unknown() {
         // Ra and Rb are source registers, Rt is the destintation.
         format LoadIndexOp {
             87: lbzx({{ Rt = Mem_ub; }});
-            52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
+            52: lbarx({{ Rt = Mem_ub; }},
+                      {{ Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
             279: lhzx({{ Rt = Mem_uh; }});
             343: lhax({{ Rt = Mem_sh; }});
-            116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
+            116: lharx({{ Rt = Mem_uh;}},
+                       {{  Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
             23: lwzx({{ Rt = Mem_uw; }});
             341: lwax({{ Rt = Mem_sw; }});
-            20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
+            20: lwarx({{ Rt = Mem_uw; }},
+                      {{ Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
             21: ldx({{ Rt = Mem; }});
-            84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
+            84: ldarx({{ Rt = Mem_ud; }},
+                      {{ Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
             532: ldbrx({{ Rt = swap_byte(Mem); }});
             535: lfsx({{ Ft_sf = Mem_sf; }});
             599: lfdx({{ Ft = Mem_df; }});
@@ -344,8 +348,9 @@ decode PO default Unknown::unknown() {
         format StoreIndexOp {
             215: stbx({{ Mem_ub = Rs_ub; }});
             694: stbcx({{
-                bool store_performed = false;
                 Mem_ub = Rs_ub;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 1) {
                         if (RsvAddr == EA) {
@@ -361,8 +366,9 @@ decode PO default Unknown::unknown() {
             }});
             407: sthx({{ Mem_uh = Rs_uh; }});
             726: sthcx({{
-                bool store_performed = false;
                 Mem_uh = Rs_uh;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 2) {
                         if (RsvAddr == EA) {
@@ -379,8 +385,9 @@ decode PO default Unknown::unknown() {
             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
             151: stwx({{ Mem_uw = Rs_uw; }});
             150: stwcx({{
-                bool store_performed = false;
                 Mem_uw = Rs_uw;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 4) {
                         if (RsvAddr == EA) {
@@ -397,8 +404,9 @@ decode PO default Unknown::unknown() {
             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
             149: stdx({{ Mem = Rs }});
             214: stdcx({{
-                bool store_performed = false;
                 Mem = Rs;
+            }}, {{
+                bool store_performed = false;
                 if (Rsv) {
                     if (RsvLen == 8) {
                         if (RsvAddr == EA) {

diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 743ac61231042eed237af7c21e0ecb5200438ad6..599674ff01fb48bb654489224177bb01bfab84f6 100644 (file)
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -82,6 +82,7 @@ def template LoadExecute {{
         }
 
         if (fault == NoFault) {
+            %(update_code)s;
             %(op_wb)s;
         }
 
@@ -120,9 +121,8 @@ def template LoadCompleteAcc {{
         Msr msr = xc->readMiscReg(MISCREG_MSR);
 
         %(op_decl)s;
-        %(op_rd)s;
-
         EA = pkt->req->getVaddr();
+        %(op_rd)s;
 
         if (msr.le)
             getMemLE(pkt, Mem, traceData);
@@ -134,7 +134,8 @@ def template LoadCompleteAcc {{
         }
 
         if (fault == NoFault) {
-          %(op_wb)s;
+            %(update_code)s;
+            %(op_wb)s;
         }
 
         return fault;
@@ -167,6 +168,7 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
+            %(update_code)s;
             %(op_wb)s;
         }
 
@@ -199,11 +201,6 @@ def template StoreInitiateAcc {{
                                      NULL);
         }
 
-        // Need to write back any potential address register update
-        if (fault == NoFault) {
-            %(op_wb)s;
-        }
-
         return fault;
     }
 }};
@@ -213,7 +210,20 @@ def template StoreCompleteAcc {{
     Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
                                       Trace::InstRecord *traceData) const
     {
-        return NoFault;
+        M5_VAR_USED Addr EA;
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        EA = pkt->req->getVaddr();
+        %(op_rd)s;
+
+        // Need to write back any potential address register update
+        if (fault == NoFault) {
+            %(update_code)s;
+            %(op_wb)s;
+        }
+
+        return fault;
     }
 }};
 
@@ -224,19 +234,22 @@ def template StoreCompleteAcc {{
 // dependence on Ra.
 let {{
 
-def GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, base,
+def GenMemOp(name, Name, memacc_code, update_code, ea_code, ea_code_ra0, base,
              load_or_store, mem_flags = [], inst_flags = []):
 
     # First the version where Ra is non-zero
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code,
+                      memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = base,
                       decode_template = CheckRaDecode,
                       exec_template_base = load_or_store)
 
     # Now another version where Ra == 0
     (header_output_ra0, decoder_output_ra0, _, exec_output_ra0) = \
-        LoadStoreBase(name, Name + 'RaZero', ea_code_ra0, memacc_code,
+        LoadStoreBase(name, Name + 'RaZero', ea_code_ra0,
+                      memacc_code, update_code,
                       mem_flags, inst_flags,
                       base_class = base,
                       exec_template_base = load_or_store)
@@ -250,20 +263,22 @@ def GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, base,
 }};
 
 
-def format LoadIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }},
+def format LoadIndexOp(memacc_code, update_code = {{ }},
+                       ea_code = {{ EA = Ra + Rb; }},
                        ea_code_ra0 = {{ EA = Rb; }},
                        mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, update_code, ea_code, ea_code_ra0,
                  'MemIndexOp', 'Load', mem_flags, inst_flags)
 }};
 
 
-def format StoreIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }},
+def format StoreIndexOp(memacc_code, update_code = {{ }},
+                        ea_code = {{ EA = Ra + Rb; }},
                         ea_code_ra0 = {{ EA = Rb; }},
                         mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, update_code, ea_code, ea_code_ra0,
                  'MemIndexOp', 'Store', mem_flags, inst_flags)
 }};
 
@@ -272,11 +287,12 @@ def format LoadIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }},
                              mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemIndexOp',
                       decode_template = CheckRaRtDecode,
                       exec_template_base = 'Load')
@@ -287,11 +303,12 @@ def format StoreIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }},
                               mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemIndexOp',
                       decode_template = CheckRaZeroDecode,
                       exec_template_base = 'Store')
@@ -302,7 +319,7 @@ def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                       ea_code_ra0 = {{ EA = disp; }},
                       mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, '', ea_code, ea_code_ra0,
                  'MemDispOp', 'Load', mem_flags, inst_flags)
 }};
 
@@ -311,7 +328,7 @@ def format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                        ea_code_ra0 = {{ EA = disp; }},
                        mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, '', ea_code, ea_code_ra0,
                  'MemDispOp', 'Store', mem_flags, inst_flags)
 }};
 
@@ -321,7 +338,7 @@ def format LoadDispShiftOp(memacc_code,
                            ea_code_ra0 = {{ EA = (disp << 2); }},
                            mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, '', ea_code, ea_code_ra0,
                  'MemDispShiftOp', 'Load', mem_flags, inst_flags)
 }};
 
@@ -331,7 +348,7 @@ def format StoreDispShiftOp(memacc_code,
                             ea_code_ra0 = {{ EA = (disp << 2); }},
                             mem_flags = [], inst_flags = []) {{
     (header_output, decoder_output, decode_block, exec_output) = \
-        GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+        GenMemOp(name, Name, memacc_code, '', ea_code, ea_code_ra0,
                  'MemDispShiftOp', 'Store', mem_flags, inst_flags)
 }};
 
@@ -340,11 +357,12 @@ def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                             mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemDispOp',
                       decode_template = CheckRaRtDecode,
                       exec_template_base = 'Load')
@@ -355,11 +373,12 @@ def format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
                              mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemDispOp',
                       decode_template = CheckRaZeroDecode,
                       exec_template_base = 'Store')
@@ -371,11 +390,12 @@ def format LoadDispShiftUpdateOp(memacc_code,
                                  mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemDispShiftOp',
                       decode_template = CheckRaRtDecode,
                       exec_template_base = 'Load')
@@ -387,11 +407,12 @@ def format StoreDispShiftUpdateOp(memacc_code,
                                   mem_flags = [], inst_flags = []) {{
 
     # Add in the update code
-    memacc_code += 'Ra = EA;'
+    update_code = 'Ra = EA;'
 
     # Generate the class
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                      mem_flags, inst_flags,
                       base_class = 'MemDispShiftOp',
                       decode_template = CheckRaZeroDecode,
                       exec_template_base = 'Store')

diff --git a/src/arch/power/isa/formats/util.isa b/src/arch/power/isa/formats/util.isa
index f836a1d691f68fb372091efca380e04771c9b84e..ccb1254ec270ecbba138f3193366fd91c5cf466b 100644 (file)
--- a/src/arch/power/isa/formats/util.isa
+++ b/src/arch/power/isa/formats/util.isa
@@ -145,8 +145,8 @@ def template CheckRaZeroDecode {{
 
 let {{
 
-def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-                  base_class = 'MemOp',
+def LoadStoreBase(name, Name, ea_code, memacc_code, update_code,
+                  mem_flags, inst_flags, base_class = 'MemOp',
                   decode_template = BasicDecode, exec_template_base = ''):
     # Make sure flags are in lists (convert to lists if not).
     mem_flags = makeList(mem_flags)
@@ -155,7 +155,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
     # Generate InstObjParams for the memory access.
     iop = InstObjParams(name, Name, base_class,
                         {'ea_code': ea_code,
-                         'memacc_code': memacc_code},
+                         'memacc_code': memacc_code,
+                         'update_code': update_code},
                         inst_flags)
 
     if mem_flags: