DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
};
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
};
static const struct bfin_dev_layout bf537_dev[] =
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
DEVICE (0, 0x20, "bfin_emac/eth_phy"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
_DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
_DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
_DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
_DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
- DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@h"),
+ DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
};
static const struct bfin_dmac_layout bf561_dmac[] =
{
DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
- DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@f"),
+ DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
- DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@g"),
+ DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
};
static const struct bfin_dmac_layout bf592_dmac[] =
{
}
else if (!strncmp (dev->dev, "bfin_gpio", 9))
{
+ char port = 'a' + strtol(&dev->dev[10], NULL, 0);
sim_hw_parse (sd, "/core/%s > mask_a port%c_irq_a /core/bfin_sic",
- dev->dev, dev->dev[10]);
+ dev->dev, port);
sim_hw_parse (sd, "/core/%s > mask_b port%c_irq_b /core/bfin_sic",
- dev->dev, dev->dev[10]);
+ dev->dev, port);
}
}