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diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 642375996fe28d1ac8ea6aa8d2b7b93f0c31f6d8..881e6acd3a95de1635b13c6aa4603a3cd380ad45 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -96,7 +96,7 @@ Some examples on different operation widths:
 Mode types:
 
 * **predicate zeroing** (sz, dz) if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.
-* **ffirst* or data-dependent fail-on-first: see separate section.
+* **ffirst** or data-dependent fail-on-first: see separate section.
 * **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element (CR0) however is still stored in the CR regfile.  This scheme does not apply to crops (crand, cror).