wishbone/SRAM: make read_only emited verilog code compatible with all tools

Quartus was not able to implement ROM correctly, see #228

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index c874eeb48a83b7eccf03c8df3606a5a297363ce9..dc242f443185110975f3c4451c592445d8ba59cc 100644 (file)
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -653,7 +653,8 @@ class SRAM(Module):
         ###
 
         # memory
-        port = self.mem.get_port(write_capable=not read_only, we_granularity=8)
+        port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
+            mode=READ_FIRST if read_only else WRITE_FIRST)
         self.specials += self.mem, port
         # generate write enable signal
         if not read_only: