Bugfixes for empty signal vectors

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 4223ebe3b6e7f0cbe0484d32a34ab74caa563167..34d0f9244ddabbceadd44f1fdef25fc2ee1f49d9 100644 (file)
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -217,6 +217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        assign_map.apply(a); \
                        if (a.is_fully_const()) { \
                                a.optimize(); \
+                               if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
                                RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
                                RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \
                                                cell->parameters["\\A_SIGNED"].as_bool(), false, \
@@ -232,6 +233,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        assign_map.apply(a), assign_map.apply(b); \
                        if (a.is_fully_const() && b.is_fully_const()) { \
                                a.optimize(), b.optimize(); \
+                               if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
+                               if (b.chunks.empty()) b.chunks.push_back(RTLIL::SigChunk()); \
                                RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \
                                                cell->parameters["\\A_SIGNED"].as_bool(), \
                                                cell->parameters["\\B_SIGNED"].as_bool(), \