add temporary SV pseudocode
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Jul 2021 17:12:13 +0000 (18:12 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Jul 2021 17:12:13 +0000 (18:12 +0100)
openpower/isa/simplev.mdwn
src/openpower/decoder/power_enums.py

index e2482b37492d5c1ccfe8058326cf29959b37111c..843c45edf38be3f8512b83bdb4c628f1d24f8656 100644 (file)
@@ -33,3 +33,28 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
+# svremap
+
+SVM-Form
+
+* svstate SVxd, SVyd, SVRM
+
+Pseudo-code:
+
+    # hack: clear out all SVSHAPEs and set them up for multiply
+    SVSHAPE0[0:31] <- [0] * 32
+    SVSHAPE1[0:31] <- [0] * 32
+    SVSHAPE2[0:31] <- [0] * 32
+    SVSHAPE3[0:31] <- [0] * 32
+    # set up FRT and FRB
+    SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
+    SVSHAPE3[0:5] <- (0b0 || SVxd)   # xdim
+    # set up FRA
+    SVSHAPE0[0:5] <- (0b0 || SVxd)   # xdim
+    SVSHAPE0[6:11] <- (0b0 || SVyd)  # ydim
+    SVSHAPE0[18:20] <- 0b010          # permute y,x,z
+
+Special Registers Altered:
+
+    None
+
index 37f14d1ed076c5ad066e123ac537c9ab5a652ba0..1b6586395cb5cf414d25727856b7558a0b768f31 100644 (file)
@@ -277,6 +277,7 @@ _insns = [
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
+    "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",