move footnote

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index c4c3650cd603ab2e10b881c51c06fedcac4a5f65..68d38ca5e3fe293c40c94eb4e24ab5b8080f4eb4 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -123,9 +123,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * No new Interrupt types are required.
   (**No modifications to existing Power ISA are required either**).
 * GPR FPR and CR Field Register numbers are extended to 128.
-  A future version may extend to 256 or beyond [^extend]
- (A future version or other Stakeholder *may* wish to drop Simple-V
-  onto VSX: this would be a separate RFC)
+  A future version may extend to 256 or beyond [^extend][^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,
   currently named "SVP64-Single" [^likeext001]
@@ -547,4 +545,4 @@ operations.
 [^pseudorewrite]: elwidth overrides does however mean that all SFS / SFFS pseudocode will need rewriting to be in terms of XLEN. This has the indirect side-effect of automatically making a 32-bit Scalar Power ISA Specification possible, as well as a future 128-bit one (Cross-reference: RISC-V RV32 and RV128
 [^only2]: reminder that this proposal only needs 75% of two POs for Scalar instructions. The rest of EXT200-263 is for general use.
 [^ext001]: Recall that EXT100 to EXT163 is for Public v3.1 64-bit-augmented Operations prefixed by EXT001, for which, from Section 1.6.3, bit 6 is set to 1.  This concept is where the above scheme originated. Section 1.6.3 uses the term "defined word" to refer to pre-existing EXT000-EXT063 32-bit instructions so prefixed to create the new numbering EXT100-EXT163, respectively
-
+[^futurevsx]: A future version or other Stakeholder *may* wish to drop Simple-V onto VSX: this would be a separate RFC