#define IMM_ENABLE CPU.imm_enable
#define IMM (IMM_ENABLE ? \
- (((uhalf)IMM_H << 16) | (uhalf)IMM_L) : \
+ (((unsigned_2)IMM_H << 16) | (unsigned_2)IMM_L) : \
(imm_unsigned ? \
(0xFFFF & IMM_L) : \
(IMM_L & 0x8000 ? \
#define MEM_RD_BYTE(X) sim_core_read_1 (cpu, 0, read_map, X)
#define MEM_RD_HALF(X) sim_core_read_2 (cpu, 0, read_map, X)
#define MEM_RD_WORD(X) sim_core_read_4 (cpu, 0, read_map, X)
-#define MEM_RD_UBYTE(X) (ubyte) MEM_RD_BYTE(X)
-#define MEM_RD_UHALF(X) (uhalf) MEM_RD_HALF(X)
-#define MEM_RD_UWORD(X) (uword) MEM_RD_WORD(X)
+#define MEM_RD_UBYTE(X) (unsigned_1) MEM_RD_BYTE(X)
+#define MEM_RD_UHALF(X) (unsigned_2) MEM_RD_HALF(X)
+#define MEM_RD_UWORD(X) (unsigned_4) MEM_RD_WORD(X)
#define MEM_WR_BYTE(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
#define MEM_WR_HALF(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
#define C_rd ((MSR & 0x4) >> 2)
#define C_wr(D) MSR = (D ? MSR | 0x80000004 : MSR & 0x7FFFFFFB)
-#define C_calc(X, Y, C) ((((uword)Y == MAX_WORD) && (C == 1)) ? \
+#define C_calc(X, Y, C) ((((unsigned_4)Y == MAX_WORD) && (C == 1)) ? \
1 : \
- ((MAX_WORD - (uword)X) < ((uword)Y + C)))
+ ((MAX_WORD - (unsigned_4)X) < ((unsigned_4)Y + C)))
#define BIP_MASK 0x00000008
#define CARRY_MASK 0x00000004
#define MAX_WORD 0xFFFFFFFF
#define MICROBLAZE_HALT_INST 0xb8000000
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-
#endif /* MICROBLAZE_H */
INSTRUCTION(bsrl,
0x11,
INST_TYPE_RD_RA_RB,
- RD = (uword)RA >> RB;
+ RD = (unsigned_4)RA >> RB;
PC += INST_SIZE)
INSTRUCTION(bsra,
0x11,
INST_TYPE_RD_RA_RB,
- RD = (word)RA >> RB;
+ RD = (signed_4)RA >> RB;
PC += INST_SIZE)
INSTRUCTION(bsll,
0x11,
INST_TYPE_RD_RA_RB,
- RD = (uword)RA << RB;
+ RD = (unsigned_4)RA << RB;
PC += INST_SIZE)
INSTRUCTION(idiv,
0x12,
INST_TYPE_RD_RA_RB,
- RD = (word) RB / (word) RA;
+ RD = (signed_4) RB / (signed_4) RA;
PC += INST_SIZE)
INSTRUCTION(idivu,
0x12,
INST_TYPE_RD_RA_RB,
- RD = (uword) RB / (uword) RA;
+ RD = (unsigned_4) RB / (unsigned_4) RA;
PC += INST_SIZE)
INSTRUCTION(muli,
INSTRUCTION(bsrli,
0x19,
INST_TYPE_RD_RA_IMM5,
- RD = (uword)RA >> (IMM & 0x1F);
+ RD = (unsigned_4)RA >> (IMM & 0x1F);
PC += INST_SIZE)
INSTRUCTION(bsrai,
0x19,
INST_TYPE_RD_RA_IMM5,
- RD = (word)RA >> (IMM & 0x1F);
+ RD = (signed_4)RA >> (IMM & 0x1F);
PC += INST_SIZE)
INSTRUCTION(bslli,
0x19,
INST_TYPE_RD_RA_IMM5,
- RD = (uword)RA << (IMM & 0x1F);
+ RD = (unsigned_4)RA << (IMM & 0x1F);
PC += INST_SIZE)
INSTRUCTION(get,
0x24,
INST_TYPE_RD_RA,
CARRY = (RA & 0x1);
- RD = ((((int) (RA >> 1)) & 0x7FFFFFFF) | (uword)(C_rd << 31));
+ RD = ((((int) (RA >> 1)) & 0x7FFFFFFF) | (unsigned_4)(C_rd << 31));
C_wr(CARRY);
PC += INST_SIZE)
0x24,
INST_TYPE_RD_RA,
CARRY = (RA & 0x1);
- RD = (uword) ((RA >> 1) & 0x7FFFFFFF);
+ RD = (unsigned_4) ((RA >> 1) & 0x7FFFFFFF);
C_wr(CARRY);
PC += INST_SIZE)