config: Bump DRAM sweep bus speed to match DDR4 config

This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.

diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 5981d59dd4d82c2b83c95f3ad2c9dc92b6a20a7a..c1ee0ceca3aadc6212af2318417ee7576bb07131 100644 (file)
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -67,11 +67,11 @@ if args:
 # at the moment we stay with the default open-adaptive page policy,
 # and address mapping
 
-# start with the system itself, using a multi-layer 1 GHz
+# start with the system itself, using a multi-layer 1.5 GHz
 # bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle)
-# which amounts to 12.8 GByte/s per layer and thus per port
+# which amounts to 19.2 GByte/s per layer and thus per port
 system = System(membus = NoncoherentBus(width = 16))
-system.clk_domain = SrcClockDomain(clock = '1GHz',
+system.clk_domain = SrcClockDomain(clock = '1.5GHz',
                                    voltage_domain =
                                    VoltageDomain(voltage = '1V'))