set name of DFI interface to ecp5phy in ECP5DDRPHY

diff --git a/gram/dfii.py b/gram/dfii.py
index a1f5ad494681f10d1465b0e7db2e6003d902171c..f9d4de528b5df3b4c3a56fcd309a170569cd13ad 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -59,7 +59,7 @@ class PhaseInjector(Elaboratable):
 
 class DFIInjector(Elaboratable):
     def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1):
-        print ("nranks", nranks, "nphases", nphases)
+        print ("nranks", nranks, "nphases", nphases, "addressbits", addressbits)
         self._nranks = nranks
 
         self._inti = dfi.Interface(addressbits, bankbits,

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 672d8b2c56ebe215dcc836d76cd681f80ce7060d..f35b760945d27fd8c9aabf93f7931bce956287de 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -143,7 +143,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         if hasattr(self.pads, "cs") and hasattr(self.pads.cs, "o0"):
             nranks = len(self.pads.cs.o0)
         databits = len(self.pads.dq.io)
-        self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
+        self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4,
+                             name="ecp5phy")
 
         # PHY settings -----------------------------------------------------------------------------
         tck = 1/(2*self._sys_clk_freq)