(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index d46bdcab93e896442a97e22d9ad4e54b6b172c5d..49d5609e6010ff84a844ff29dc0dc91e4883543f 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -40,7 +40,8 @@ other Vector-aware Branch Conditional instructions are a high priority
 for 3D GPU workloads.
 
 The `BI` field of Branch Conditional operations is five bits, in scalar
-v3.0B this would select one bit of the 32 bit CR.  In SVP64 there are
+v3.0B this would select one bit of the 32 bit CR,
+comprising eight CR Fields of 4 bits each.  In SVP64 there are
 16 32 bit CRs, containing 128 4-bit CR Fields.  Therefore, the 2 LSBs of
 `BI` select the bit from the CR Field (EQ LT GT SO), and the top 3 bits
 are extended to either scalar or vector and to select CR Fields 0..127