+2017-11-16 Chung-Ju Wu <jasonwucj@gmail.com>
+ Kito Cheng <kito.cheng@gmail.com>
+
+ * config/nds32/nds32.opt: Add mext-perf, mext-perf2, mext-string.
+ * config/nds32/nds32.opt: Refine the layout.
+ * config/nds32/nds32.c (TARGET_EXT_PERF, TARGET_EXT_PERF2,
+ TARGET_EXT_STRING): Support new options.
+ * config/nds32/nds32.h: Likewise.
+ * config/nds32/nds32.md: Likewise.
+ * config/nds32/nds32-predicates.c: Likewise.
+ * config/nds32/constraints.md: Likewise.
+ * common/config/nds32/nds32-common.c: Likewise.
+
2017-11-16 Julia Koval <julia.koval@intel.com>
PR target/82983
Other MASK_XXX flags are set individually.
By default we enable
- TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
- TARGET_PERF_EXT : Generate performance extention instrcution.
- TARGET_CMOV : Generate conditional move instruction. */
+ TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
+ TARGET_EXT_PERF : Generate performance extention instrcution.
+ TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
+ TARGET_EXT_STRING : Generate string extention instrcution.
+ TARGET_CMOV : Generate conditional move instruction. */
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
(TARGET_CPU_DEFAULT \
| MASK_16_BIT \
- | MASK_PERF_EXT \
+ | MASK_EXT_PERF \
+ | MASK_EXT_PERF2 \
+ | MASK_EXT_STRING \
| MASK_CMOV)
#undef TARGET_HANDLE_OPTION
(define_constraint "Ixls"
"The immediate value 0x01"
(and (match_code "const_int")
- (match_test "TARGET_PERF_EXT && (ival == 0x1)")))
+ (match_test "TARGET_EXT_PERF && (ival == 0x1)")))
(define_constraint "Ix11"
"The immediate value 0x7ff"
(and (match_code "const_int")
- (match_test "TARGET_PERF_EXT && (ival == 0x7ff)")))
+ (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
(define_constraint "Ibms"
"The immediate value with power of 2"
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
/* 'bclr' is a performance extension instruction. */
- return (TARGET_PERF_EXT && (one_bit_count == 1));
+ return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'bset' instruction can be used with IVAL. */
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
/* 'bset' is a performance extension instruction. */
- return (TARGET_PERF_EXT && (one_bit_count == 1));
+ return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'btgl' instruction can be used with IVAL. */
one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
/* 'btgl' is a performance extension instruction. */
- return (TARGET_PERF_EXT && (one_bit_count == 1));
+ return (TARGET_EXT_PERF && (one_bit_count == 1));
}
/* Function to check if 'bitci' instruction can be used with IVAL. */
((TARGET_CMOV) ? "Yes"
: "No"));
fprintf (asm_out_file, "\t! Use performance extension\t: %s\n",
- ((TARGET_PERF_EXT) ? "Yes"
+ ((TARGET_EXT_PERF) ? "Yes"
: "No"));
+ fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n",
+ ((TARGET_EXT_PERF2) ? "Yes"
+ : "No"));
+ fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n",
+ ((TARGET_EXT_STRING) ? "Yes"
+ : "No"));
fprintf (asm_out_file, "\t! ------------------------------------\n");
{
/* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */
target_flags |= MASK_REDUCED_REGS;
- /* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT. */
- target_flags &= ~MASK_PERF_EXT;
+ /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */
+ target_flags &= ~MASK_EXT_PERF;
+ /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */
+ target_flags &= ~MASK_EXT_PERF2;
+ /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */
+ target_flags &= ~MASK_EXT_STRING;
}
/* See if we are using reduced-set registers:
builtin_define ("__NDS32_REDUCED_REGS__"); \
if (TARGET_CMOV) \
builtin_define ("__NDS32_CMOV__"); \
- if (TARGET_PERF_EXT) \
- builtin_define ("__NDS32_PERF_EXT__"); \
+ if (TARGET_EXT_PERF) \
+ builtin_define ("__NDS32_EXT_PERF__"); \
+ if (TARGET_EXT_PERF2) \
+ builtin_define ("__NDS32_EXT_PERF2__"); \
+ if (TARGET_EXT_STRING) \
+ builtin_define ("__NDS32_EXT_STRING__"); \
if (TARGET_16_BIT) \
builtin_define ("__NDS32_16_BIT__"); \
if (TARGET_GP_DIRECT) \
(define_insn "clzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(clz:SI (match_operand:SI 1 "register_operand" " r")))]
- "TARGET_PERF_EXT"
+ "TARGET_EXT_PERF"
"clz\t%0, %1"
[(set_attr "type" "alu")
(set_attr "length" "4")])
[(set (match_operand:SI 0 "register_operand" "=r")
(smax:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
- "TARGET_PERF_EXT"
+ "TARGET_EXT_PERF"
"max\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])
[(set (match_operand:SI 0 "register_operand" "=r")
(smin:SI (match_operand:SI 1 "register_operand" " r")
(match_operand:SI 2 "register_operand" " r")))]
- "TARGET_PERF_EXT"
+ "TARGET_EXT_PERF"
"min\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])
(zero_extract:SI (match_operand:SI 1 "register_operand" " r")
(const_int 1)
(match_operand:SI 2 "immediate_operand" " Iu05")))]
- "TARGET_PERF_EXT"
+ "TARGET_EXT_PERF"
"btst\t%0, %1, %2"
[(set_attr "type" "alu")
(set_attr "length" "4")])
HeaderInclude
config/nds32/nds32-opts.h
-mbig-endian
-Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
+; ---------------------------------------------------------------
+; The following options are designed for aliasing and compatibility options.
+
+EB
+Target RejectNegative Alias(mbig-endian)
Generate code in big-endian mode.
-mlittle-endian
-Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
+EL
+Target RejectNegative Alias(mlittle-endian)
Generate code in little-endian mode.
+; ---------------------------------------------------------------
+
mreduced-regs
Target Report RejectNegative Negative(mfull-regs) Mask(REDUCED_REGS)
Use reduced-set registers for register allocation.
Target Report RejectNegative Negative(mreduced-regs) InverseMask(REDUCED_REGS)
Use full-set registers for register allocation.
+; ---------------------------------------------------------------
+
+mbig-endian
+Target Undocumented RejectNegative Negative(mlittle-endian) Mask(BIG_ENDIAN)
+Generate code in big-endian mode.
+
+mlittle-endian
+Target Undocumented RejectNegative Negative(mbig-endian) InverseMask(BIG_ENDIAN)
+Generate code in little-endian mode.
+
+
mcmov
Target Report Mask(CMOV)
Generate conditional move instructions.
-mperf-ext
-Target Report Mask(PERF_EXT)
+mext-perf
+Target Report Mask(EXT_PERF)
Generate performance extension instructions.
+mext-perf2
+Target Report Mask(EXT_PERF2)
+Generate performance extension version 2 instructions.
+
+mext-string
+Target Report Mask(EXT_STRING)
+Generate string extension instructions.
+
mv3push
Target Report Mask(V3PUSH)
Generate v3 push25/pop25 instructions.
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