Revert "write_xaiger to pad, not abc9_ops -prep_holes"

This reverts commit b5f60e055d07579a2d4f23fc053ca030f103f377.

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c01adde3d4a64ecc493d85386488446701f6f47a..a9680525d8a2941207de86740f5035e16dde114f 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -318,14 +318,13 @@ struct XAigerWriter
                                }
                        }
 
+                       // Fully pad all unused input connections of this box cell with S0
+                       // Fully pad all undriven output connections of this box cell with anonymous wires
                        for (auto port_name : r.first->second) {
                                auto w = box_module->wire(port_name);
                                log_assert(w);
-
-                               SigSpec rhs = cell->connections_.at(port_name, SigSpec());
-                               if (w->port_input) {
-                                       // Add padding to fill entire port
-                                       rhs.append(SigSpec(State::Sx, GetSize(w)-GetSize(rhs)));
+                               auto rhs = cell->getPort(port_name);
+                               if (w->port_input)
                                        for (auto b : rhs) {
                                                SigBit I = sigmap(b);
                                                if (b == RTLIL::Sx)
@@ -339,18 +338,14 @@ struct XAigerWriter
                                                co_bits.emplace_back(b);
                                                unused_bits.erase(I);
                                        }
-                               }
-                               if (w->port_output) {
-                                       // Add padding to fill entire port
-                                       rhs.append(SigSpec(State::Sx, GetSize(w)-GetSize(rhs)));
-                                       for (const auto &b : rhs) {
+                               if (w->port_output)
+                                       for (const auto &b : rhs.bits()) {
                                                SigBit O = sigmap(b);
                                                if (O != b)
                                                        alias_map[O] = b;
                                                ci_bits.emplace_back(b);
                                                undriven_bits.erase(O);
                                        }
-                               }
                        }
 
                        // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
@@ -417,11 +412,8 @@ struct XAigerWriter
 
                for (auto &bit : ci_bits) {
                        aig_m++, aig_i++;
-                       // State::Sx if padding
-                       if (bit != State::Sx) {
-                               log_assert(!aig_map.count(bit));
-                               aig_map[bit] = 2*aig_m;
-                       }
+                       log_assert(!aig_map.count(bit));
+                       aig_map[bit] = 2*aig_m;
                }
 
                for (auto bit : co_bits) {
@@ -609,6 +601,8 @@ struct XAigerWriter
                        f.write(buffer_str.data(), buffer_str.size());
 
                        if (holes_module) {
+                               log_module(holes_module);
+
                                std::stringstream a_buffer;
                                XAigerWriter writer(holes_module, true /* holes_mode */);
                                writer.write_aiger(a_buffer, false /*ascii_mode*/);

diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc
index e6e4e3e72941cb643665d89aba5c2fbcdabba954..c01feedb69fb842cb31de0061672e9ef9d6eb781 100644 (file)
--- a/passes/techmap/abc9_map.cc
+++ b/passes/techmap/abc9_map.cc
@@ -438,19 +438,24 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                        if (existing_cell) {
                                cell->parameters = existing_cell->parameters;
                                cell->attributes = existing_cell->attributes;
-                               if (cell->attributes.erase("\\abc9_box_seq")) {
-                                       module->swap_names(cell, existing_cell);
-                                       module->remove(existing_cell);
-                               }
                        }
                        else {
                                cell->parameters = mapped_cell->parameters;
                                cell->attributes = mapped_cell->attributes;
                        }
 
+                       auto abc9_box = cell->attributes.erase("\\abc9_box_seq");
+                       if (abc9_box) {
+                               module->swap_names(cell, existing_cell);
+                               module->remove(existing_cell);
+                       }
                        RTLIL::Module* box_module = design->module(mapped_cell->type);
                        auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
                        for (auto &conn : mapped_cell->connections()) {
+                               // Skip entire box ports composed entirely of padding only
+                               if (abc9_box && conn.second.is_wire() && conn.second.as_wire()->get_bool_attribute(ID(abc9_padding)))
+                                       continue;
+
                                RTLIL::SigSpec newsig;
                                for (auto c : conn.second.chunks()) {
                                        if (c.width == 0)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 730431ebf7152d39e45656c0de08f30d815df176..ab5aa9f8d15532858306ed8577bde7d0405d8db0 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -254,6 +254,45 @@ void prep_holes(RTLIL::Module *module, bool dff)
                RTLIL::Module* box_module = design->module(cell->type);
                if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
                        continue;
+
+               bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
+
+               // Fully pad all unused input connections of this box cell with S0
+               // Fully pad all undriven output connections of this box cell with anonymous wires
+               for (const auto &port_name : box_module->ports) {
+                       RTLIL::Wire* w = box_module->wire(port_name);
+                       log_assert(w);
+                       auto it = cell->connections_.find(port_name);
+                       if (w->port_input) {
+                               RTLIL::SigSpec rhs;
+                               if (it != cell->connections_.end()) {
+                                       if (GetSize(it->second) < GetSize(w))
+                                               it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
+                                       rhs = it->second;
+                               }
+                               else {
+                                       rhs = RTLIL::SigSpec(State::S0, GetSize(w));
+                                       cell->setPort(port_name, rhs);
+                               }
+                       }
+                       if (w->port_output) {
+                               RTLIL::SigSpec rhs;
+                               auto it = cell->connections_.find(w->name);
+                               if (it != cell->connections_.end()) {
+                                       if (GetSize(it->second) < GetSize(w))
+                                               it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
+                                       rhs = it->second;
+                               }
+                               else {
+                                       Wire *wire = module->addWire(NEW_ID, GetSize(w));
+                                       if (blackbox)
+                                               wire->set_bool_attribute(ID(abc9_padding));
+                                       rhs = wire;
+                                       cell->setPort(port_name, rhs);
+                               }
+                       }
+               }
+
                cell->attributes["\\abc9_box_seq"] = box_list.size();
                box_list.emplace_back(cell);
        }