X86: Implement the LTR instruction.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 3cdfa48bb56009439a32daae5820ee8a9ae080f1..67845fe8df88504910c78cf0c1c8e28ba07a27dd 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -94,7 +94,7 @@
                     0x0: sldt_Mw_or_Rv();
                     0x1: str_Mw_or_Rv();
                     0x2: lldt_Mw_or_Rv();
-                    0x3: ltr_Mw_or_Rv();
+                    0x3: Inst::LTR(Ew);
                     0x4: verr_Mw_or_Rv();
                     0x5: verw_Mw_or_Rv();
                     //0x6: jmpe_Ev(); // IA-64

diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py
index 49d8eb110729da2a9ef45cecd39d09a7f13877f8..c2bb46b7ce6f7532bb927dd6d43b96997993fde7 100644 (file)
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -168,6 +168,54 @@ def macroop LIDT_16_P
     wrlimit idtr, t1
 };
 
+def macroop LTR_R
+{
+    chks reg, t0, TRCheck
+    limm t4, 0
+    srli t4, reg, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks reg, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, reg
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_M
+{
+    ld t5, seg, sib, disp, dataSize=2
+    chks t5, t0, TRCheck
+    limm t4, 0
+    srli t4, t5, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks t5, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, t5
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
+def macroop LTR_P
+{
+    rdip t7
+    ld t5, seg, riprel, disp, dataSize=2
+    chks t5, t0, TRCheck
+    limm t4, 0
+    srli t4, t5, 3, dataSize=2
+    ldst t1, tsg, [8, t4, t0], dataSize=8
+    ld t2, tsg, [8, t4, t0], 8, dataSize=8
+    chks t5, t1, TSSCheck
+    wrdh t3, t1, t2
+    wrdl tr, t1, t5
+    wrbase tr, t3, dataSize=8
+    ori t1, t1, (1 << 9)
+    st t1, tsg, [8, t4, t0], dataSize=8
+};
+
 def macroop SWAPGS
 {
     rdval t1, kernel_gs_base, dataSize=8