RISC-V: Remove RV128-only fmv instructions

As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.

gas/ChangeLog:

	* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
	* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
	* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
	MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.

diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
new file mode 100644 (file)
index 0000000..2913a1a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64iq
+#source: fmv.x.q-rv64-fail.s
+#error_output: fmv.x.q-rv64-fail.l

diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
new file mode 100644 (file)
index 0000000..9fb1f8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*Error: unrecognized opcode `fmv\.x\.q a0,fa0'
+.*Error: unrecognized opcode `fmv\.q\.x fa0,a0'

diff --git a/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
new file mode 100644 (file)
index 0000000..320a557
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fmv.x.q-rv64-fail.s
@@ -0,0 +1,2 @@
+fmv.x.q a0, fa0
+fmv.q.x fa0, a0

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ecbb8b8487b4865db1e081d163bbbe23f8ee0ca8..2e867965e12cdd5ef2596297b78adea186d34870 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -389,8 +389,6 @@
 #define MASK_FCVT_L_Q  0xfff0007f
 #define MATCH_FCVT_LU_Q 0xc6300053
 #define MASK_FCVT_LU_Q  0xfff0007f
-#define MATCH_FMV_X_Q 0xe6000053
-#define MASK_FMV_X_Q  0xfff0707f
 #define MATCH_FCLASS_Q 0xe6001053
 #define MASK_FCLASS_Q  0xfff0707f
 #define MATCH_FCVT_S_W 0xd0000053
@@ -421,8 +419,6 @@
 #define MASK_FCVT_Q_L  0xfff0007f
 #define MATCH_FCVT_Q_LU 0xd6300053
 #define MASK_FCVT_Q_LU  0xfff0007f
-#define MATCH_FMV_Q_X 0xf6000053
-#define MASK_FMV_Q_X  0xfff0707f
 #define MATCH_CLZ 0x60001013
 #define MASK_CLZ  0xfff0707f
 #define MATCH_CTZ 0x60101013
@@ -2650,7 +2646,6 @@ DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
-DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
@@ -2666,7 +2661,6 @@ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
-DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
 DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
 DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7524be7feae6e8a8f378f4626383da163608c743..eaba3cb46ccbcf577d6ac0bf492137140d58599b 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -825,8 +825,6 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fle.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
 {"fgt.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
 {"fge.q",      0, INSN_CLASS_Q_OR_ZQINX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fmv.x.q",   64, INSN_CLASS_Q,   "d,S",       MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
-{"fmv.q.x",   64, INSN_CLASS_Q,   "D,s",       MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
 {"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
 {"fcvt.l.q",  64, INSN_CLASS_Q_OR_ZQINX,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
 {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },