#include "sid.h"
#include "util/u_memory.h"
+#include "util/u_suballoc.h"
#include "util/u_upload_mgr.h"
FREE(desc->list);
}
+static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
+ unsigned *out_offset, struct r600_resource **out_buf) {
+ uint64_t va;
+
+ u_suballocator_alloc(sctx->ce_suballocator, size, out_offset,
+ (struct pipe_resource**)out_buf);
+ if (!out_buf)
+ return false;
+
+ va = (*out_buf)->gpu_address + *out_offset;
+
+ radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
+ radeon_emit(sctx->ce_ib, ce_offset);
+ radeon_emit(sctx->ce_ib, size / 4);
+ radeon_emit(sctx->ce_ib, va);
+ radeon_emit(sctx->ce_ib, va >> 32);
+
+ sctx->ce_need_synchronization = true;
+ return true;
+}
+
+
static bool si_upload_descriptors(struct si_context *sctx,
struct si_descriptors *desc)
{
#include "radeon/radeon_llvm_emit.h"
#include "radeon/radeon_uvd.h"
#include "util/u_memory.h"
+#include "util/u_suballoc.h"
#include "vl/vl_decoder.h"
/*
si_release_all_descriptors(sctx);
+ if (sctx->ce_suballocator)
+ u_suballocator_destroy(sctx->ce_suballocator);
+
pipe_resource_reference(&sctx->esgs_ring, NULL);
pipe_resource_reference(&sctx->gsvs_ring, NULL);
pipe_resource_reference(&sctx->tf_ring, NULL);
if (!sctx->ce_preamble_ib)
goto fail;
}
+
+ sctx->ce_suballocator =
+ u_suballocator_create(&sctx->b.b, 1024 * 1024,
+ 64, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT, FALSE);
+ if (!sctx->ce_suballocator)
+ goto fail;
}
sctx->b.gfx.flush = si_context_gfx_flush;
struct si_compute;
struct hash_table;
+struct u_suballocator;
struct si_screen {
struct r600_common_screen b;
void *custom_blend_dcc_decompress;
void *pstipple_sampler_state;
struct si_screen *screen;
+
struct radeon_winsys_cs *ce_ib;
struct radeon_winsys_cs *ce_preamble_ib;
bool ce_need_synchronization;
+ struct u_suballocator *ce_suballocator;
struct pipe_fence_handle *last_gfx_fence;
struct si_shader_ctx_state fixed_func_tcs_shader;