radeonsi: Add CE uploader.
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thu, 10 Mar 2016 20:23:49 +0000 (21:23 +0100)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tue, 19 Apr 2016 16:10:30 +0000 (18:10 +0200)
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_descriptors.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/radeonsi/si_pipe.h

index c41923dabc82cc10cf7e9cac9bafd71cd97e10fd..e9458ece0bc65241dde4afa5dfb82e1328a13469 100644 (file)
@@ -61,6 +61,7 @@
 #include "sid.h"
 
 #include "util/u_memory.h"
+#include "util/u_suballoc.h"
 #include "util/u_upload_mgr.h"
 
 
@@ -133,6 +134,28 @@ static void si_release_descriptors(struct si_descriptors *desc)
        FREE(desc->list);
 }
 
+static bool si_ce_upload(struct si_context *sctx, unsigned ce_offset, unsigned size,
+                        unsigned *out_offset, struct r600_resource **out_buf) {
+       uint64_t va;
+
+       u_suballocator_alloc(sctx->ce_suballocator, size, out_offset,
+                            (struct pipe_resource**)out_buf);
+       if (!out_buf)
+                       return false;
+
+       va = (*out_buf)->gpu_address + *out_offset;
+
+       radeon_emit(sctx->ce_ib, PKT3(PKT3_DUMP_CONST_RAM, 3, 0));
+       radeon_emit(sctx->ce_ib, ce_offset);
+       radeon_emit(sctx->ce_ib, size / 4);
+       radeon_emit(sctx->ce_ib, va);
+       radeon_emit(sctx->ce_ib, va >> 32);
+
+       sctx->ce_need_synchronization = true;
+       return true;
+}
+
+
 static bool si_upload_descriptors(struct si_context *sctx,
                                  struct si_descriptors *desc)
 {
index ddfa59fd128504977aa7f6ee3dd151b89029fee2..ca07331187f3924eb1151d9e1ba0216ada0028ba 100644 (file)
@@ -29,6 +29,7 @@
 #include "radeon/radeon_llvm_emit.h"
 #include "radeon/radeon_uvd.h"
 #include "util/u_memory.h"
+#include "util/u_suballoc.h"
 #include "vl/vl_decoder.h"
 
 /*
@@ -41,6 +42,9 @@ static void si_destroy_context(struct pipe_context *context)
 
        si_release_all_descriptors(sctx);
 
+       if (sctx->ce_suballocator)
+               u_suballocator_destroy(sctx->ce_suballocator);
+
        pipe_resource_reference(&sctx->esgs_ring, NULL);
        pipe_resource_reference(&sctx->gsvs_ring, NULL);
        pipe_resource_reference(&sctx->tf_ring, NULL);
@@ -155,6 +159,13 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
                        if (!sctx->ce_preamble_ib)
                                goto fail;
                }
+
+               sctx->ce_suballocator =
+                               u_suballocator_create(&sctx->b.b, 1024 * 1024,
+                                                     64, PIPE_BIND_CUSTOM,
+                                                     PIPE_USAGE_DEFAULT, FALSE);
+               if (!sctx->ce_suballocator)
+                       goto fail;
        }
 
        sctx->b.gfx.flush = si_context_gfx_flush;
index b3f5ed5e8d8a0d5f5cae160c6676d4c04c1a1e7e..1540c7f1014bc304b71a7cb10d0e8a955a1adf55 100644 (file)
@@ -80,6 +80,7 @@
 
 struct si_compute;
 struct hash_table;
+struct u_suballocator;
 
 struct si_screen {
        struct r600_common_screen       b;
@@ -191,9 +192,11 @@ struct si_context {
        void                            *custom_blend_dcc_decompress;
        void                            *pstipple_sampler_state;
        struct si_screen                *screen;
+
        struct radeon_winsys_cs         *ce_ib;
        struct radeon_winsys_cs         *ce_preamble_ib;
        bool                            ce_need_synchronization;
+       struct u_suballocator           *ce_suballocator;
 
        struct pipe_fence_handle        *last_gfx_fence;
        struct si_shader_ctx_state      fixed_func_tcs_shader;