test_caller_bcd: mark addg6s test as slowpoke

diff --git a/src/openpower/decoder/isa/test_caller_bcd.py b/src/openpower/decoder/isa/test_caller_bcd.py
index 5c6deca6a5f995957292b86c7dfccb7d5a0b4973..d1a0ee3fb97e0935d43838a7117b7d84f24c5325 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_bcd.py
+++ b/src/openpower/decoder/isa/test_caller_bcd.py
@@ -15,7 +15,7 @@ from openpower.decoder.isa.all import ISA
 
 
 # addg6s product limitations
-ADDG6S_PRODUCT_LIMIT = 16
+ADDG6S_PRODUCT_LIMIT = 2
 
 
 # PowerISA Version 3.0C Book 1 App. B, Table 129
@@ -316,6 +316,7 @@ class BCDTestCase(FHDLTestCase):
                 mapping[bcd] = dpd
         self.run_tst("cbcdtd", mapping)
 
+    @unittest.skip("slowpoke")
     def test_addg6s(self):
         def half_adder(a, b):
             (a, b) = map(bool, [a, b])